CC2564MODACMOG datasheet(21/62 Pages) TI1

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CC2564MODN, CC2564MODA

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SWRS160D – FEBRUARY 2014 – REVISED DECEMBER 2015

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Long and short frames

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Different data sizes, order, and positions

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High flexibility to support a variety of codecs

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Bus sharing: Data_Out is in Hi-Z state when the interface is not transmitting voice data.

5.8.1

Hardware Interface

The interface includes four signals:

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Clock: configurable direction (input or output)

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Frame_Sync and Word_Sync: configurable direction (input or output)

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Data_In: input

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Data_Out: output or 3-state

The module can be the master of the interface when generating the Clock and Frame_Sync signals or the

slave when receiving these two signals.

For slave mode, clock input frequencies of up to 15 MHz are supported. At clock rates above 12 MHz, the

maximum data burst size is 32 bits.

For master mode, the module can generate any clock frequency between 64 kHz and 4.096 MHz.

5.8.2

I2S

When the codec interface is configured to support the I2S protocol, these settings are recommended:

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Bidirectional, full-duplex interface

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Two time slots per frame: time slot-0 for the left channel audio data; and time slot-1 for the right

channel audio data

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Each time slot is configurable up to 40 serial clock cycles long, and the frame is configurable up to 80

serial clock cycles long.

5.8.3

Data Format

The data format is fully configurable:

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The data length can be from 8 to 320 bits in 1-bit increments when working with 2 channels, or up to

640 bits when working with 1 channel. The data length can be set independently for each channel.

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The data position within a frame is also configurable within 1 clock (bit) resolution and can be set

independently (relative to the edge of the Frame_Sync signal) for each channel.

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The Data_In and Data_Out bit order can be configured independently. For example, Data_In can start

with the most significant bit (MSB); Data_Out can start with the least significant bit (LSB). Each

channel is separately configurable. The inverse bit order (that is, LSB first) is supported only for

sample sizes up to 24 bits.

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Data_In and Data_Out are not required to be the same length.

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The Data_Out line is configured to Hi-Z output between data words. Data_Out can also be set for

permanent Hi-Z, regardless of the data output. This configuration allows the module to be a bus slave

in a multislave PCM environment. At power up, Data_Out is configured as Hi-Z.

5.8.4

Frame Idle Period

The codec interface handles frame idle periods, in which the clock pauses and becomes 0 at the end of

the frame, after all data are transferred.

The module supports frame idle periods both as master and slave of the codec bus.

When the module is the master of the interface, the frame idle period is configurable. There are two

configurable parameters:

Detailed Description

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