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CC2564MODACMOG Datasheet(PDF) 13 Page - Texas Instruments |
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CC2564MODACMOG Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 62 page ![]() AUD_CLK AUD_OUT / FSYNC_OUT AUD_IN / FSYNC_IN t ih t op t is T clk T w td_aud_swrs064 T w CC2564MODN, CC2564MODA www.ti.com SWRS160D – FEBRUARY 2014 – REVISED DECEMBER 2015 4.7.3.2 PCM Figure 4-4 shows the interface timing for the PCM. Figure 4-4. PCM Interface Timing Table 4-5 lists the associated PCM master parameters. Table 4-5. PCM Master Symbol PARAMETER CONDITION MIN MAX UNIT Tclk Cycle time 244.14 15625 (4.096 MHz) (64 kHz) Tw High or low pulse width 50% of Tclk min tis AUD_IN setup time 25 ns tih AUD_IN hold time 0 top AUD_OUT propagation time 40-pF load 0 10 top FSYNC_OUT propagation time 40-pF load 0 10 Table 4-6 lists the associated PCM slave parameters. Table 4-6. PCM Slave SYMBOL PARAMETER CONDITION MIN MAX UNIT Tclk Cycle time 66.67 (15 MHz) Tw High or low pulse width 40% of Tclk Tis AUD_IN setup time 8 ns Tih AUD_IN hold time 0 tis AUD_FSYNC setup time 8 tih AUD_FSYNC hold time 0 top AUD_OUT propagation time 40-pF load 0 21 Copyright © 2014–2015, Texas Instruments Incorporated Specifications 13 Submit Documentation Feedback Product Folder Links: CC2564MODN CC2564MODA |
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