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AM1705DPTP3 Datasheet(PDF) 68 Page - Texas Instruments |
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AM1705DPTP3 Datasheet(HTML) 68 Page - Texas Instruments |
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68 / 165 page ![]() AM1705 SPRS657E – FEBRUARY 2010 – REVISED JUNE 2014 www.ti.com 6.11.2 Interfacing to SDRAM The EMIFB supports a glueless interface to SDRAM devices with the following characteristics: • Pre-charge bit is A[10] • Supports 8, 9, 10 or 11 column address bits • Supports up to 13 row address bits • Supports 1, 2 or 4 internal banks Table 6-20 shows the supported SDRAM configurations for EMIFB. Table 6-20. EMIFB Supported SDRAM Configurations(1) SDRAM Memory Memory Number of EMIFB Data Total Memory Total Memory Data Bus Rows Columns Banks Density Memories Bus Size (Mbits) (Mbytes) Width (Mbits) (bits) 1 16 13 8 1 32 4 32 1 16 13 8 2 64 8 64 1 16 13 8 4 128 16 128 1 16 13 9 1 64 8 64 1 16 13 9 2 128 16 128 1 16 13 9 4 256 32 256 16 1 16 13 10 1 128 16 128 1 16 13 10 2 256 32 256 1 16 13 10 4 512 64 512 1 16 13 11 1 256 32 256 1 16 13 11 2 512 64 512 1 16 13 11 4 1024 128 1024 2 16 13 8 1 32 4 16 2 16 13 8 2 64 8 32 2 16 13 8 4 128 16 64 2 16 13 9 1 64 8 32 2 16 13 9 2 128 16 64 2 16 13 9 4 256 32 128 8 2 16 13 10 1 128 16 64 2 16 13 10 2 256 32 128 2 16 13 10 4 512 64 256 2 16 13 11 1 256 32 128 2 16 13 11 2 512 64 256 2 16 13 11 4 1024 128 512 (1) The shaded cells indicate configurations that are possible on the EMIFA interface but as of this writing SDRAM memories capable of supporting these densities are not available in the market. 68 Peripheral Information and Electrical Specifications Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM1705 |
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