DP83902A datasheet(49/70 Pages) NSC

49 / 70 page

130 Bus Arbitration and Timing (Continued)

SLAVE MODE TIMING

When CS is low the ST-NIC becomes a bus slave The CPU

can then read or write any internal registers All register

accesses are byte wide The timing for register access is

shown below The host CPU accesses internal registers

with four address lines RA0 – RA3 SRD and SWR strobes

ADS0 is used to latch the address when interfacing to a

multiplexed address data bus Since the ST-NIC may be a

local bus master when the host CPU attempts to read or

write to the controller an ACK line is used to hold off the

CPU until the ST-NIC leaves master mode Some number of

BSCK cycles is also required to allow the ST-NIC to syn-

chronize to the read or write cycles

Write to Register

TLF11157 – 31

Read from Register

TLF11157 – 32

TIME BETWEEN CHIP SELECTS

The ST-NIC requires that successive chip selects be no

closer than 4 bus clocks (BSCK) together If the condition is

violated the ST-NIC may glitch ACK CPUs that operate

from pipelined instructions (ie 386) or have a cache (ie

486) can execute consecutive IO cycles very quickly The

solution is to delay the execution of consecutive IO cycles

by either breaking the pipeline or forcing the CPU to access

outside its cache

Time between Chip Selects

TLF11157 – 63

DP83902A Datasheet(PDF) 49 Page - National Semiconductor (TI)