DP83905AVQB datasheet(4/80 Pages) NSC

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20 Pin Description

Pin No

Pin Name

Type

Description

ISA BUS INTERFACE PINS

94–97

SA0–SA1 9

LATCHED ADDRESS BUS

Low-order 20 bits of the system’s 24 bit address bus

These lines are enabled onto the bus by the system when BALE is high and are

99–106

TTL

Iatched when BALE returns Iow These bits are used to decode accesses to the

108–115

ATLANTIC Controller’s IO map and to the boot PROM In addition they are used to

decode accesses to the ATLANTIC Controller’s memory in shared memory mode

76–82

LA17–LA23

UNLATCHED ADDRESS BUS

High order 7 bits of the 24-bit system address bus

These Iines are valid on the falling edge of BALE These bits are used to decode

TTL

accesses to the ATLANTIC Controller’s memory in shared memory mode

127 128

SD0–SD15

SYSTEM DATA BUS

16-bit system data bus Used to transfer data between the

system and the ATLANTIC Controller

130 131

3SH

133 134

136 137

73 72

70 69

67 66

64 63

BALE

BUS ADDRESS LATCH ENABLE

This signal indicates when the system address

lines are valid

TTL

SBHE

SYSTEM BUS HIGH ENABLE

This signal indicates that the system expects a

transfer on the upper byte lane

TTL

M16

16-BIT MEMORY TRANSFER

In 16-bit shared memory mode this signal indicates

that the ATLANTIC Controller has decoded an address within the 128 kbyte space

OCH

that it occupies part of

IO16

16-BIT IO TRANSFER

In IO mode this signal indicates that the ATLANTIC

Controller is responding to a 16-bit IO access by driving 16-bits of data on the bus

OCH

MWR

MEMORY WRITE STROBE

Strobe from system to write to ATLANTIC Controller’s

memory map

This pin should be connected to allow the CHRDY fix in 16-bit IO mode

TTL

to operate correctly (See Section 60)

MRD

MEMORY READ STROBE

Strobe from system to read from ATLANTIC Controller’s

memory map

This pin should be connected to allow the CHRDY fix in 16-bit IO mode

TTL

to operate correctly (See Section 60)

119

SMRD

LOW MEMORY STROBES

In Memory mode these signals strobe memory transfers

in the same manner as MRD and MWR except that these signals only occur if the

120

SMWR

TTL

access is to the lowest 1 Megabyte This partial address decode means that these

signals can be used in an 8-bit slot to properly decode an access to this area

The

ATLANTIC Controller will use MRD and MWR in 16-bit Memory mode and will use

SMRD and SMWR in Memory mode when DWID is low (8-bit mode) SMRD and

SMWR are also used to access the BOOT PROM

118

IOWR

IO WRITE STROBE

Strobe from system to write to the ATLANTIC Controller’s IO

map

TTL

117

IORD

IO READ STROBE

Strobe from system to read from the ATLANTIC Controller’s

IO map

TTL

126

RESET

This signal is output by the system to reset all devices on the bus

TTL

Driver Types are I e Input O e Output IO e Bi-directional Output OCH e Open Collector 3SH e TRI-STATE Output TTL e TTL Compatible AUI e

Attachment Unit Interface TPI e Twisted Pair Interface LED e LED Drive MOS e CMOS Level Compatible XTAL e Crystal

DP83905AVQB Datasheet(PDF) 4 Page - National Semiconductor (TI)

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