DP83905AVQB datasheet(44/80 Pages) NSC

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60 Operation of ATLANTIC Controller (Continued)

the CRC generator Packets with improper CRC will be re-

jected The AUTODlN II (X32 a X26 a X23 a X22 a X16 a

X12 a X11 a X10 a X8 a X7 a X5 a X4 a X2a X1 a 1)

polynomial is used for the CRC calculations

62 BUFFER MEMORY ACCESS CONTROL (DMA)

The buffer memory control capabilities of the ATLANTIC

Controller greatly simplify the use of the ATLANTIC Con-

troller in typical configurations The local DMA channel

transfers data between the FIFO and memory On transmis-

sion the packet is DMA’d from memory to the FIFO in

bursts Should a collision occur (up to 15 times) the packet

is re-transmitted with no processor intervention On recep-

tion packets are moved via DMA from the FIFO to the re-

ceive buffer ring (as explained below)

A Remote DMA channel is also provided on the ATLANTIC

Controller to accomplish transfers between a buffer memory

and an internal Data Port when using the ATLANTIC Con-

troller in IO Mode This Remote DMA channel is not used

when the ATLANTIC Controller is used in a shared Memo-

ry mode In this second mode the buffer memory is dual

ported and directly mapped into the system memory In this

mode the system CPU directly accesses the RAM under

software control to transfer packet data

The following sections describe the operation of the Local

DMA channel for packet reception which is used in both

modes For Shared Memory mode the description of the

Remote DMA does not apply

For reference an example configuration using the ATLAN-

TIC Controller is shown in

Figure 27

TLF11498 – 24

FIGURE 27 ATLANTIC Controller Bus Architecture

DP83905AVQB Datasheet(PDF) 44 Page - National Semiconductor (TI)