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DP83905AVQB Datasheet(PDF) 71 Page - National Semiconductor (TI) |
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DP83905AVQB Datasheet(HTML) 71 Page - National Semiconductor (TI) |
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71 / 80 page ![]() 80 Preliminary Switching Characteristics Memory Support Bus Accesses (for IO port or FIFO transfers) TLF11498 – 53 8-Bit 16-Bit Symbol Description Transfers Transfers Units Min Max Min Max T1 MSA1b15 Valid before RCS 30 30 ns Asserted (Note 1) T2 MSA1b15 Valid before 20 20 ns MSRDbWR Asserted T3 MSRDbWR Width 70 70 ns T4 RCS and MSA1b15 Valid to 105 105 ns MSWR Deasserted (Note 1) T5 MSA1b15 Valid after 10 10 ns MSRDbWR Deasserted T6 RCS Held after MSRDbWR 10 10 ns Deasserted (Note 1) T7 RCS and MSA1b15 Valid to 100 100 ns MSD0b15 Valid (Note 1) T8 Read Data Hold from MSRD Deasserted 0 0 ns T9 Write Data Set-Up to MSWR Deasserted 50 50 ns T10 Write Data Held from MSWR Deasserted 10 10 ns T11 Time Between Transfers 4 4 bcyc T12 Minimum Bus Clock High Time (bch) 20 20 ns T13 Minimum Bus Clock Low Time (bcl) 20 20 ns T14 Minimum Bus Clock Cycle Time (bcyc) 50 50 ns Note 1 In 8-bit mode RCS refers to RCS1 only In 16-bit mode RCS refers to both RCS1 and RCS2 71 |
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