DP83905AVQB datasheet(65/80 Pages) NSC

65 / 80 page

60 Operation of ATLANTIC Controller (Continued)

8-Bit Shared Memory Mode Write Bus Timing with DWID High

TLF11498 – 48

This is the type of cycle used to write 8 bits to buffer RAM in shared memory mode when DWID is high These accesses are

entirely asynchronous with the ATLANTIC Controller responding when it decodes the correct address on LA17 – 23 SA0 – 19

and a IORD If AEN is high the cycle will be ignored CHRDY is deasserted if the ATLANTIC Controller is not ready to respond

and asserted when ready If it is ready immediately CHRDY is not deasserted The 816-bit in Control Register 2 must be set to

allow generation of M16 This will be generated whenever the LA17 – 23 lines match the corresponding values in Control

Register 2 It will therefore be generated for a full 128 kbytes of address space although the ATLANTIC Controller will occupy

less than that It may be preferable to only set the 816-bit for the duration of a transfer to the buffer RAM The ATLANTIC

Controller will also compare the address line programmed in Control Register 1 before allowing accesses to buffer RAM and

therefore do a complete decode The system indicates that this is an 8-bit transfer by not asserting SBHE for an even address

SA0 low or by accessing an odd address SA0 high If the 816-bit is low the ATLANTIC Controller will only read data from

SD0 – 7 Even addresses will use RCS1 and MSD0 – 7 odd addresses will use RCS2 and MSD8 – 15 If 816-bit is high the

ATLANTIC Controller can read from either SD0 – 7 or SD8 – 15 Even addresses are read from SD0 – 7 and written to RAM using

RCS1 and MSD0 – 7 Odd addresses are read from SD8 – 15 and written to RAM using RCS2 and MSD8 – 15

DP83905AVQB Datasheet(PDF) 65 Page - National Semiconductor (TI)