ADF7020 datasheet(12/40 Pages) AD

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ADF7020

Preliminary Technical Data

Rev. PrH | Page 12 of 40

Analog Lock Detect

This N-channel open-drain lock detect should be operated with

an external pull-up resistor of 10 kΩ nominal. When a lock has

been detected, this output is high with narrow low-going pulses.

Voltage Regulators

The ADF7020 contains four regulators to supply stable voltages

to the part. The nominal regulator voltage is 2.3 V. Each

regulator should have a 100 nF capacitor connected between

VREG and GND. When CE is high, the regulators and other

associated circuitry are powered on, drawing a total supply

current of 2 mA. Bringing the chip-enable pin low disables the

regulators, reduces the supply current to less than 1 µA, and

erases all values held in the registers. The serial interface

operates off a regulator supply; therefore, to write to the part,

the user must have CE high and the regulator voltage must be

stabilized. Regulator status (VREG4) can be monitored using

the regulator ready signal from MUXOUT.

Loop Filter

The loop filter integrates the current pulses from the charge

pump to form a voltage that tunes the output of the VCO to the

desired frequency. It also attenuates spurious levels generated by

the PLL. A typical loop filter design is shown in Figure 8.

CHARGE

PUMP OUT

VCO

Figure 8. Typical Loop Filter Configuration

In FSK, the loop should be designed so that the loop bandwidth

(LBW) is approximately five times the data rate. Widening the

LBW excessively reduces the time spent jumping between

frequencies, but can cause insufficient spurious attenuation.

For ASK systems, a wider LBW is recommended. The sudden

large transition between two power levels might result in VCO

pulling and can cause a wider output spectrum than is desired.

By widening the LBW to more than 10 times the data rate, the

amount of VCO pulling is reduced, because the loop settles

quickly back to the correct frequency. The wider LBW might

restrict the output power and data rate of ASK-based systems

compared with FSK-based systems.

Narrow-loop bandwidths can result in the loop taking long

periods of time to attain lock. Careful design of the loop filter is

critical to obtaining accurate FSK/GFSK modulation.

For GFSK, it is recommended that an LBW of 2.0 to 2.5 times

the data rate be used to ensure that sufficient samples are taken

of the input data while filtering system noise. The free design

tool ADIsimPLL can be used to design loop filters for the

ADF7020.

N Counter

The feedback divider in the ADF7020 PLL consists of an 8-bit

integer counter and a 14-bit Σ-∆ fractional-N divider. The

integer counter is the standard pulse-swallow type common in

PLLs. This sets the minimum integer divide value to 31. The

fractional divide value gives very fine resolution at the output,

where the output frequency of the PLL is calculated as

FOUT =

XTAL

× (

Integer-N +

-N

Fractional

)

VCO

THIRD-ORDER

Σ-∆ MODULATOR

PFD/

CHARGE

PUMP

INTEGER-N

FRACTIONAL-N

REFERENCE IN

Figure 9. Fractional-N PLL

The combination of the integer-N (maximum = 255) and the

fractional-N (maximum = 16383/16384) give a maximum N

divider of 255 + 1. Therefore, the minimum usable PFD is

PDFMIN [Hz] = Maximum Required Output Frequency/(255 + 1)

For example, when operating in the European 868 MHz to

870 MHz band, PFDMIN equals 3.4 MHz.

Voltage Controlled Oscillator (VCO)

To minimize spurious emissions, the on-chip VCO operates

from 1732 MHz to 1856 MHz. The VCO signal is then divided

by 2 to give the required frequency for the transmitter and the

required LO frequency for the receiver.

The VCO should be recentered, depending on the required

frequency of operation, by programming the VCO adjust bits

R1_DB(20:21).

The VCO is enabled as part of the PLL by the PLL-enable bit,

R0_DB28.

A further frequency divide-by-2 is included to allow operation

in the lower 433 MHz and 460 MHz bands. To enable operation

in the these bands, R1_DB13 should be set to 1. The VCO needs

an external 22 nF between the VCO and the regulator to reduce

internal noise.

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