ADF7020 datasheet(19/40 Pages) AD

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Preliminary Technical Data

ADF7020

Rev. PrH | Page 19 of 40

LINEAR FSK DEMODULATOR

A block diagram of the linear FSK demodulator is shown in

Figure 17.

SLICER

FREQUENCY

LEVEL

LIMITER

MUX 1

ADC RSSI OUTPUT

LINEAR DISCRIMINATOR

DB(6:15)

FREQUENCY

READBACK

AND

AFC LOOP

Rx DATA

Figure 17. Block Diagram of Frequency Measurement System and

ASK.OOK/Linear FSK Demodulator

This method of frequency demodulation is useful when very

short preamble length is required and the system protocol

cannot support the overhead of the settling time of the internal

feedback AFC loop settling.

A digital frequency discriminator provides an output signal that

is linearly proportional to the frequency of the limiter outputs.

The discriminator output is then filtered and averaged using a

combined averaging filter and envelope detector. The demodu-

lated FSK data is recovered by threshold-detecting the output of

the averaging filter, as shown in Figure 17. In this mode, the

slicer output shown in Figure 17 is routed to the data synchro-

nizer PLL for clock synchronization. To enable the linear FSK

demodulator, set Bits R4_DB(4:5) to [00].

The 3 dB bandwidth of the postdemodulation filter is set in the

same way as the FSK correlator/demodulator, which is set in

R4_DB(6:15) and is defined as

CLK

DEMOD

Setting

Demod

Post

CUTOFF

where:

FCUTOFF is the target 3 dB bandwidth in Hz of the

postdemodulator filter.

DEMOD_CLK is as defined in the Register 3—Receiver Clock

ASK/OOK Operation

ASK/OOK demodulation is activated by setting Bits

R4_DB(4:5) to [10].

Digital filtering and envelope detecting the digitized RSSI input

via MUX 1, as shown in Figure 17, perform ASK/OOK

demodulation. The bandwidth of the digital filter must be

optimized to remove any excess noise without causing ISI in the

received ASK/OOK signal.

The 3 dB bandwidth of this filter is typically set at approxi-

mately 0.75 times the user data rate and is assigned by R4

_DB(6:15) as

Post_Demod_BW_Setting =

DEMOD_CLK

CUTOFF

×2

where FCUTOFF is the target 3 dB bandwidth in Hz of the

postdemodulator filter.

AFC SECTION

The ADF7020 supports a real-time AFC loop, which is used to

remove frequency errors that can arise due to mismatches

between the transmit and receive crystals. This uses the

frequency discriminator block, as described in the Linear FSK

Demodulator section (see Figure 17). The discriminator output

is filtered and averaged to remove the FSK frequency

modulation using a combined averaging filter and envelope

detector. In FSK mode, the output of the envelope detector

provides an estimate of the average IF frequency.

Two methods of AFC, external and internal, are supported on

the ADF7020 (in FSK mode only).

External AFC

The user reads back the frequency information through the

ADF7020 serial port and applies a frequency correction value to

the fractional-N synthesizer’s N divider.

The frequency information is obtained by reading the 16-bit

signed AFC_readback, as described in the Readback Format

section, and applying the following formula:

FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/215

Note that while the AFC_READBACK value is a signed number,

under normal operating conditions it is positive. In the absence

of frequency errors, the FREQ_RB value is equal to the IF

frequency of 200 kHz.

Internal AFC

The ADF7020 supports a real-time internal automatic

frequency control loop. In this mode, an internal control loop

automatically monitors the frequency error and adjusts the

synthesizer N divider using an internal PI control loop.

The internal AFC control loop parameters are controlled in

R11_DB20 to 1. A scaling coefficient must also be entered,

based on the crystal frequency in use. This is set up in

R11_DB(4:19) and should be calculated using

AFC_Scaling_Coefficient = (500 × 224)/XTAL

Therefore, using a 10 MHz XTAL yields an AFC scaling

coefficient of 839.

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