ADF7020

Preliminary Technical Data

Rev. PrH | Page 30 of 40

REGISTER 3—RECEIVER CLOCK REGISTER

FS8

0

0

.

1

1

FS7

0

0

.

1

1

FS3

0

0

.

1

1

...

...

...

...

...

...

FS2

0

1

.

1

1

FS1

1

0

.

0

1

CDR_CLK_DIVIDE

1

2

.

254

255

BK2

0

0

1

BK1

0

1

x

BBOS_CLK_DIVIDE

4

8

16

SK8

0

0

.

1

1

SK7

0

0

.

1

1

SK3

0

0

.

1

1

...

...

...

...

...

...

SK2

0

1

.

1

1

SK1

1

0

.

0

1

SEQ_CLK_DIVIDE

1

2

.

254

255

OK2

0

0

1

1

OK1

0

1

0

1

DEMOD_CLK_DIVIDE

4

1

2

3

SEQUENCER CLOCK DIVIDE

CDR CLOCK DIVIDE

ADDRESS

BITS

Figure 31.

Notes:

1.

Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where:

DIVIDE

CLK

BBOS

XTAL

CLK

BBOS

_

_

_

=

2.

The demodulator clock (DEMOD_CLK) must be < 12 MHz for FSK and < 6 MHz for ASK, where:

DIVIDE

CLK

DEMOD

XTAL

CLK

DEMOD

_

_

_

=

3.

Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 × data rate), where:

DIVIDE

CLK

CDR

CLK

DEMOD

CLK

CDR

_

_

_

_

=

Note that this might affect your choice of XTAL, depending on the desired data rate.

4.

The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz for FSK and close to 40 kHz for ASK:

DIVIDE

CLK

SEQ

XTAL

CLK

SEQ

_

_

_

=