DS90C124, DS90C241

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SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013

DS90C241 and DS90C124 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and

Deserializer

Check for Samples: DS90C124, DS90C241

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FEATURES

DESCRIPTION

The DS90C241 and DS90C124 chipset translates a

2

•

5-MHz to 35-MHz clock embedded and DC-

24-bit parallel bus into a fully transparent data and

Balancing 24:1 and 1:24 data transmissions

control LVDS serial stream with embedded clock

•

User defined pre-emphasis driving ability

information.

This

single

serial

stream

simplifies

through external resistor on LVDS outputs and

transferring a 24-bit bus over PCB traces or over

capable to drive up to 10-meter shielded

cable by eliminating the skew problems between

twisted-pair cable

parallel data and clock paths. It saves system cost by

narrowing data paths, which in turn reduces PCB

•

User-selectable clock edge for parallel data on

layers, cable width, and connector size and pins.

both transmitter and receiver

The DS90C241 and DS90C124 incorporate LVDS

•

Internal DC balancing encode and decode –

signaling on the high-speed I/O. LVDS provides a

Supports AC-coupling interface with no

low-power and low-noise environment for reliably

external coding required

transferring data over a serial transmission path. By

•

Individual power-down controls for both

optimizing the serializer output edge rate for the

transmitter and receiver

operating frequency range, EMI is further reduced.

•

Embedded clock CDR (clock and data

In addition, the device features pre-emphasis to boost

recovery) on receiver and no external source

signals over longer distances using lossy cables.

of reference clock needed

Internal

DC

balanced

encoding

and

decoding

•

All codes RDL (random data lock) to support

supports AC-coupled interconnects.

live-pluggable applications

•

LOCK output flag to ensure data integrity at

receiver side

•

RDATA on receiver side

•

PTO (progressive turn-on) LVCMOS outputs to

reduce EMI and minimize SSO effects

•

All LVCMOS inputs and control pins have

internal pulldown

•

On-chip filters for PLLs on transmitter and

receiver

•

Temperature range –40°C to +105°C

•

Greater than 8-kV HBM ESD tolerant

•

Meets AEC-Q100 compliance

•

Power supply range 3.3V ± 10%

•

48-pin TQFP package

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PRODUCTION DATA information is current as of publication date.

Copyright © 2005–2013, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.