ADUC848BCP8-5 datasheet(39/108 Pages) AD

39 / 108 page

ADuC845/ADuC847/ADuC848

Rev. A | Page 39 of 108

FUNCTIONAL DESCRIPTION

ADC SFR INTERFACE

The ADCs are controlled and configured via a number of SFRs that are mentioned here and described in more detail in the following

sections.

Table 22. ADC SFR Interface

Name

Description

ADCSTAT

ADC Status Register. Holds the general status of the primary and auxiliary (ADuC845 only) ADCs.

ADCMODE

ADC Mode Register. Controls the general modes of operation for primary and auxiliary (ADuC845 only) ADCs.

ADC0CON1

Primary ADC Control Register 1. Controls the specific configuration of the primary ADC.

ADC0CON2

Primary ADC Control Register 2. Controls the specific configuration of the primary ADC.

ADC1CON

Auxiliary ADC Control Register. Controls the specific configuration of the auxiliary ADC. ADuC845 only.

Sinc Filter Register. Configures the decimation factor for the Sinc3 filter and, therefore, the primary and auxiliary (ADuC845

only) ADC update rates.

ICON

Current Source Control Register. Allows user control of the various on-chip current source options.

ADC0L/M/H

Primary ADC 24-bit (16-bit on the ADuC848) conversion result is held in these three 8-bit registers. ADC0L is not available on

the ADuC848.

ADC1L/M/H

Auxiliary ADC 24-bit conversion result is held in these two 8-bit registers. ADuC845 only.

OF0L/M/H

Primary ADC 24-bit offset calibration coefficient is held in these three 8-bit registers. OF0L is not available on the ADuC848.

OF1L/H

Auxiliary ADC 16-bit offset calibration coefficient is held in these two 8-bit registers. ADuC845 only.

GN0L/M/H

Primary ADC 24-bit gain calibration coefficient is held in these three 8-bit registers. GN0L is not available on the ADuC848.

GN1L/H

Auxiliary ADC 16-bit gain calibration coefficient is held in these two 8-bit registers. ADuC845 only.

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