ADUC848BCP8-5 datasheet(13/108 Pages) AD

13 / 108 page

ADuC845/ADuC847/ADuC848

Rev. A | Page 13 of 108

Pin No:

52-MQFP

Pin No:

56-CSP

Mnemonic

Type1

Description

P3.7/RD

External Data Memory Read Strobe. This pin enables the data from an external

data memory to Port 0.

20, 34, 48

22, 36, 51

DVDD

Digital Supply Voltage.

21, 35, 47

23, 37,

38, 50

DGND

Digital Ground.

SCLK (I2C)

I/O

Serial Interface Clock for the I2C Interface. As an input, this pin is a Schmitt-

triggered input. A weak internal pull-up is present on this pin unless it is

outputting logic low. This pin can also be controlled in software as a digital

output pin.

SDATA

I/O

Serial Data Pin for the I2C Interface. As an input, this pin has a weak internal pull-

up present unless it is outputting logic low.

28–31,

36–39

30–33,

39–42

P2.0–P2.7

I/O

Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have

1s written to them are pulled high by the internal pull-up resistors, and in that

state can be used as inputs. As inputs, Port 2 pins being pulled externally low

source current because of the internal pull-up resistors. Port 2 emits the middle

and high-order address bytes during accesses to the 24-bit external data

memory space.

Port 2 pins also have the various secondary functions described below.

P2.0/SCLOCK (SPI)

Serial Interface Clock for the SPI Interface. As an input this pin is a Schmitt-

triggered input. A weak internal pull-up is present on this pin unless it is

outputting logic low.

P2.1/MOSI

Serial Master Output/Slave Input Data for the SPI Interface. A strong internal

pull-up is present on this pin when the SPI interface outputs a logic high. A

strong internal pull-down is present on this pin when the SPI interface outputs a

logic low.

P2.2/MISO

Master Input/Slave Output for the SPI Interface. A weak pull-up is present on this

input pin.

P2.3/SS/T2

Slave Select Input for the SPI Interface. A weak pull-up is present on this pin.

For both package options, this pin can also be used to provide a clock input to

Timer 2. When enabled, Counter 2 is incremented in response to a negative

transition on the T2 input pin.

P2.4/T2EX

Control Input to Timer 2. When enabled, a negative transition on the T2EX input

pin causes a Timer 2 capture or reload event.

P2.5/PWM0

If the PWM is enabled, the PWM0 output appears at this pin.

P2.6/PWM1

If the PWM is enabled, the PWM1 output appears at this pin.

P2.7/PWMCLK

If the PWM is enabled, an external PWM clock can be provided at this pin.

XTAL1

Input to the Crystal Oscillator Inverter.

XTAL2

Output from the Crystal Oscillator Inverter. See the Hardware Design

Considerations section for a description.

External Access Enable, Logic Input. When held high, this input enables the

device to fetch code from internal program memory locations 0000H to F7FFH.

No external program memory access is available on the ADuC845, ADuC847, or

ADuC848. To determine the mode of code execution, the EA pin is sampled at

the end of an external RESET assertion or as part of a device power cycle. EA can

also be used as an external emulation I/O pin, and therefore the voltage level at

this pin must not be changed during normal operation because this might

cause an emulation interrupt that halts code execution.

PSEN

Program Store Enable, Logic Output. This function is not used on the ADuC845,

ADuC847, or ADuC848. This pin remains high during internal program execution.

PSEN can also be used to enable serial download mode when pulled low

through a resistor at the end of an external RESET assertion or as part of a device

power cycle.

ALE

Address Latch Enable, Logic Output. This output is used to latch the low byte

(and page byte for 24-bit data address space accesses) of the address to external

memory during external data memory access cycles. It can be disabled by

setting the PCON.4 bit in the PCON SFR.

Footnotes at end of table.

ADUC848BCP8-5 Datasheet(PDF) 13 Page - Analog Devices

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