ADUC848BCP8-5 datasheet(63/108 Pages) AD

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ADuC845/ADuC847/ADuC848

Rev. A | Page 63 of 108

Hardware Slave Mode

After reset, the ADuC845/ADuC847/ADuC848 default to

hardware slave mode. The I2C interface is enabled by clearing

the SPE bit in SPICON. Slave mode is enabled by clearing the

I2CM bit in I2CCON. The parts have a full hardware slave. In

slave mode, the I2C address is stored in the I2CADD register.

Data received or to be transmitted is stored in the I2CDAT

Once enabled in I2C slave mode, the slave controller waits for

a start condition. If the parts detect a valid start condition,

followed by a valid address, followed by the R/W bit, then the

I2CI interrupt bit is automatically set by hardware. The I2C

peripheral generates a core interrupt only if the user has pre-

configured the I2C interrupt enable bit in the IEIP2 SFR as well

as the global interrupt bit, EA, in the IE SFR. Therefore,

MOV IEIP2, #01h

;Enable I

2C Interrupt

SETB EA

An autoclear of the I2CI bit is implemented on the parts so that

this bit is cleared automatically upon read or write access to the

I2CDAT SFR.

MOV I2CDAT, A

;I2CI auto-cleared

MOV A, I2CDAT

;I2CI auto-cleared

If for any reason the user tries to clear the interrupt more than

once, that is, access the data SFR more than once per interrupt,

the I2C controller stops. The interface then must be reset by

using the I2CRS bit.

The user can choose to poll the I2CI bit or to enable the

interrupt. In the case of the interrupt, the PC counter vectors to

003BH at the end of each complete byte. For the first byte, when

the user gets to the I2CI ISR, the 7-bit address and the R/W bit

appear in the I2CDAT SFR.

The I2CTX bit contains the R/W bit sent from the master. If

I2CTX is set, the master is ready to receive a byte; therefore the

slave transmits data by writing to the I2CDAT register. If I2CTX

is cleared, the master is ready to transmit a byte; therefore the

slave receives a serial byte. Software can interrogate the state of

I2CTX to determine whether it should write to or read from

I2CDAT.

Once the part has received a valid address, hardware holds

SCLOCK low until the I2CI bit is cleared by software. This

allows the master to wait for the slave to be ready before

transmitting the clocks for the next byte.

The I2CI interrupt bit is set every time a complete data byte is

received or transmitted, provided that it is followed by a valid

ACK. If the byte is followed by a NACK, an interrupt is not

generated.

The part continues to issue interrupts for each complete data

byte transferred until a stop condition is received or the interface

is reset.

When a stop condition is received, the interface resets to a state

in which it is waiting to be addressed (idle). Similarly, if the

interface receives a NACK at the end of a sequence, it also

returns to the default idle state. The I2CRS bit can be used to

reset the I2C interface. This bit can be used to force the interface

back to the default idle state.

ADUC848BCP8-5 Datasheet(PDF) 63 Page - Analog Devices

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