ADUC848BCP8-5 datasheet(67/108 Pages) AD

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ADuC845/ADuC847/ADuC848

Rev. A | Page 67 of 108

DUAL DATA POINTERS

The parts incorporate two data pointers. The second data

pointer is a shadow data pointer and is selected via the data

pointer control SFR (DPCON). DPCON features automatic

hardware post-increment and post-decrement as well as an

automatic data pointer toggle.

DPCON—Data Pointer Control SFR

SFR Address:

A7H

Power-On Default:

00H

Bit Addressable:

Table 42. DPCON SFR Bit Designations

Bit No.

Name

Description

----

Not Implemented. Write Don’t Care.

DPT

Data Pointer Automatic Toggle Enable.

Cleared by the user to disable autoswapping of the DPTR.

Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction.

Shadow Data Pointer Mode. These bits enable extra modes of the shadow data pointer operation, allowing

more compact and more efficient code size and execution.

DP1m1

DP1m0

Behavior of the Shadow Data Pointer

8052 behavior.

DPTR is post-incremented after a MOVX or a MOVC instruction.

DPTR is post-decremented after a MOVX or MOVC instruction.

5, 4

DP1m1, DP1m0

DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction can be useful for

moving 8-bit blocks to/from 16-bit devices.)

Main Data Pointer Mode. These bits enable extra modes of the main data pointer operation, allowing more

compact and more efficient code size and execution.

DP0m1

DP0m0

Behavior of the Main Data Pointer

8052 behavior.

DPTR is post-incremented after a MOVX or a MOVC instruction.

DPTR is post-decremented after a MOVX or MOVC instruction.

3, 2

DP0m1, DP0m0

DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction is useful for

moving 8-bit blocks to/from 16-bit devices.)

----

Not Implemented. Write Don’t Care.

DPSEL

Data Pointer Select.

Cleared by the user to select the main data pointer. This means that the contents of this 24-bit register are

placed into the DPL, DPH, and DPP SFRs.

Set by the user to select the shadow data pointer. This means that the contents of a separate 24-bit register

appear in the DPL, DPH, and DPP SFRs.

Note the following:

•

The Dual Data Pointer section is the only place in which

main and shadow data pointers are distinguished.

Whenever the DPTR is mentioned elsewhere in this data

sheet, active DPTR is implied.

•

Only the MOVC/MOVX @DPTR instructions

automatically post-increment and post-decrement the

DPTR. Other MOVC/MOVX instructions, such as MOVC

PC or MOVC @Ri, do not cause the DPTR to automatically

post-increment and post-decrement.

To illustrate the operation of DPCON, the following code copies

256 bytes of code memory at Address D000H into XRAM,

starting from Address 0000H.

MOV DPTR,#0

;Main DPTR = 0

MOV DPCON,#55H

;Select shadow DPTR

;DPTR1 increment mode

;DPTR0 increment mode

;DPTR auto toggling ON

MOV DPTR,#0D000H ;DPTR = D000H

MOVELOOP: CLR A

MOVC A,@A+DPTR

;Get data

;Post Inc DPTR

;Swap to Main DPTR(Data)

MOVX @DPTR,A

;Put ACC in XRAM

;Increment main DPTR

;Swap Shadow DPTR(Code)

MOV A, DPL

JNZ MOVELOOP

ADUC848BCP8-5 Datasheet(PDF) 67 Page - Analog Devices

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