DP83932C datasheet(47/98 Pages) NSC

47 / 98 page

50 Bus Interface (Continued)

TABLE 5-1 Pin Description

(Continued)

Symbol

Driver

Direction

Description

Type

NETWORK INTERFACE PINS

(Continued)

LBK

This pin will be TRI-STATE until the DCR has been written to (See Section 432

EXBUS for more information)

EXUSR2

TRI

O Z

Loopback (LBK)

When ENDEC loopback is programmed LBK is asserted high

Although this signal is used internally by the SONIC it is also provided as an output to

the user

Extended User Output (EXUSR2)

When EXBUS has been set (see Section 432) this

pin becomes a programmable output It will remain TRI-STATE until the SONIC

becomes a bus master at which time it will be driven according to the value

programmed in the DCR2 (Section 437)

PCOMP

TRI

O Z

Packet Compression

This pin is used with the Management Bus of the DP83950

Repeater Interface Controller (RIC) The SONIC can be programmed to assert PCOMP

whenever there is a CAM match or when there is not a match The RIC uses this signal

to compress (shorten) a received packet for management purposes and to reduce

memory usage (See the DP83950 datasheet for more details on the RIC Management

Bus) The operation of this pin is controlled by bits 1 and 2 in the DCR2 register PCOMP

will remain TRI-STATE until these bits are written to This signal is asserted right after

the 4th bit of the 7th byte of the incoming packet and is deasserted one transmit clock

(TXC) after CRS is driven low

SEL

Mode Select (EXT e 0)

This pin is used to determine the voltage relationship between

TXa and TXb during idle at the primary of the isolation transformer on the network

interface When tied to VCC TXa and TXb are at equal voltages during idle When tied

to ground the voltage at TXa is positive with respect to TXb during idle on the primary

side of the isolation transformer (

Figure 6-2 )

PREJ

Packet Reject

This signal is used to reject received packets When asserted low for at

least two receive clocks (RXC) the SONIC will reject the incoming packet This pin can

be asserted up to the 2nd to the last bit of reception to reject a packet

OSCOUT

Crystal Feedback Output

This signal is used to provide clocking signals for the

internal ENDEC A crystal can be connected to this pin along with OSCIN See Section

613 for more information about using oscillators or crystals

OSCIN

Crystal Feedback Input or External Oscillator Input

This signal is used to provide

clocking signals for the internal ENDEC A crystal may be connected to this pin along

with OSCOUT or an oscillator module may be used Typically the output of an oscillator

module is connected to this pin See Section 613 for more information about using

oscillator modules or crystals

BUS INTERFACE PINS

BMODE

Bus Mode

This input enables the SONIC to be compatible with standard

microprocessor buses The level of this pin affects byte ordering (little or big endian) and

controls the operation of the bus interface control signals A high level (tied to VCC)

selects Motorola mode (big endian) and a low level (tied to ground) selects National

Intel mode (little endian) Note the alternate pin definitions for AS ADS MRW MWR

INT INT BR HOLD BG HLDA SRW SWR DSACK0 RDYo and DSACK1 RDYi

DP83932C Datasheet(PDF) 47 Page - National Semiconductor (TI)

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