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DP83932C Datasheet(PDF) 91 Page - National Semiconductor (TI) |
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DP83932C Datasheet(HTML) 91 Page - National Semiconductor (TI) |
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91 / 98 page  70 AC and DC Specifications (Continued) Number Parameter 20 MHz 25 MHz 33 MHz Units Min Max Min Max Min Max T56 CS Asynch Setup to BSCK (Notes 3 4) 8 7 6 ns T60 CS Valid to SMACK Low (Notes 2 3 4) 1 5 1 5 1 5 bcyc T63 Register Address Setup to SAS 654 ns T64 Register Address Hold from SAS 876 ns T67 SRW (Read) Setup to SAS 432 ns T69 SAS Asynch Setup to BSCK (Notes 3 4) 7 6 5 ns T69a SAS Asynch Setup to BSCK (Notes 3 5) 5 4 3 ns T74 SRW (Read) Hold from SAS 876 ns T75a BSCK to DSACK01 Low 14 12 10 ns T77 CS to DSACK01 High (Note 5) 20 18 16 ns T77a SAS to DSACK01 High (Note 5) 24 22 20 ns T77b BSCK to DSACK01 TRI-STATE (Note 5) 19 17 15 ns T78 Skew between DSACK01 332 ns T79a BSCK to SMACK High (Note 5) 19 17 15 ns T81 BSCK to SMACK Low 22 20 18 ns T82 BSCK to Register Data Valid 44 42 40 ns T85a Min CS Deassert Time (Notes 2 3) 1 1 1 bcyc T86 SAS to Register Data TRI-STATE (Note 6) 42 40 38 ns Note 1 This figure shows a slave access to the SONIC when the SONIC is idle or rather not in master mode If the SONIC is a bus master there will be some differences as noted in the Memory ArbitrationSlave Access diagram The BSCK states (T1 T2 etc) are the equivalent processor states during a slave access Note 2 bcyc e bus clock cycle time (T3) Note 3 It is not necessary to meet the setup time for CS and SAS (T56 and T69) since these signals are asynchronously sampled Meeting the setup time for these signals however makes it possible to use T60 to determine when SMACK will be asserted SAS may be asserted anytime before the next falling edge of the clock that the CS is sampled on (as shown by specification T69) For multiple register accesses CS can be held low and SAS can be used to delimit the slave cycle (T69a must be met in order to terminate and start another cycle) In this case SMACK will be asserted as soon as T69 timing is met Note 4 T60 could range from 1 bus clock minimum to 5 bus clock maximum depending on what state machine the SONIC is in when the CS signal is asserted This timing is not tested but is guaranteed by design This specification assumes that both T56 is met for CS and T69 is met for SAS T60 specification also assumes that there were no wait states in the current master mode access (if CS is asserted when SONIC is in Master Mode) If there were wait states then it would increase the T60 further Note 5 It is not necessary to meet the setup times for SAS (T69a) since this signal is asynchronously sampled Meeting the setup time for this signal however will ensure DSACK01 becomes TRI-STATE (T77b) and SMACK goes high (T79) at the falling edge of T1 Both CS and SAS could cause DSACK01 to deassert but only SAS could cause DSACK01 to become TRI-STATE Note 6 This timing value includes an RC delay inherent in the test measurement These signals typically TRI-STATE 7 ns earlier enabling other devices to drive these lines without contention 91 |
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