DP83932C datasheet(71/98 Pages) NSC

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60 Network Interfacing (Continued)

TLF10492 – 81

FIGURE 64 Crystal Connection to the SONIC

(see text)

Note 1

The OSCOUT pin is not guaranteed to provide a TTL compatible

logic output and should not be used to drive any external logic If

additional logic needs to be driven then an external oscillator

should be used as described in the following section

Note 2

The frequency marked on the crystal is usually measured with a

fixed load capacitance specified in the crystal’s data sheet The

actual load capacitance used should be the specified value minus

the stray capacitance

TABLE 6-1 Crystal Specifications

Resonant frequency

20 MHz

Tolerance (see text)

001% at 25 C

Accuracy

0005% (50 ppm) at 0 to 70 C

Fundamental Mode

Series Resistance

25X

Specified Load

Capacitance

18 pF

Type

AT cut

Circuit

Parallel Resonance

6132 Clock Oscillator Module

The SONIC also allows for an external clock oscillator to be

used The connection configuration is shown in

Figure 65

This connection requires an oscillator with the following

specifications

1 TTL or CMOS output with a 001% frequency tolerance

2 40% – 60% duty cycle (50% duty cycle preferred)

3 One CMOS loads output drive

The above assumes no other circuitry is driven In this con-

figuration the OSCOUT pin must be left open

TLF10492 – 83

FIGURE 65 Oscillator Module Connection to the SONIC

6133 PCB Layout Considerations

Care should be taken when connecting a crystal Stray ca-

pacitance (eg

from PC board traces and plated through

holes around the OSCIN and OSCOUT pins) can shift the

crystal’s frequency out of range causing the transmitted fre-

quency to exceed the 001% tolerance specified by IEEE

The layout considerations for using an external crystal are

rather straightforward The oscillator layout should locate all

components close to the OSCIN and OSCOUT pins and

should use short traces that avoid excess capacitance and

inductance A solid ground should be used to connect the

ground legs of the two capacitors

When connecting an external oscillator the only considera-

tions are to keep the oscillator module as close to the

SONIC as possible to reduce stray capacitance and induc-

tance and to give the module a clean VCC and a solid

ground

614 Power Supply Considerations

In general power supply routing and design for the SONIC

need only follow standard practices In some situations

however additional care may be necessary in the layout of

the analog supply Specifically special care may be needed

for the TXVCC RXVCC and PLLVCC power supplies and

the TXGND and ANGND In most cases the analog and

digital power supplies can be interconnected However to

ensure optimum performance of the SONIC’s analog func-

tions power supply noise should be minimized To reduce

analog supply noise any of several techniques can be used

1 Route analog supplies as a separate set of traces or

planes from the digital supplies with their own decoupling

capacitors

2 Provide noise filtering on the analog supply pins by insert-

ing a low pass filter Alternatively a ferrite bead could be

used to reduce high frequency power supply noise

3 Utilize a separate regulator to generate the analog sup-

ply

The PLLVCC pin is the a5V power supply for the phase lock

loop (PLL) of the SONIC ENDEC unit Since this is an ana-

log circuit excessive noise on the PLLVCC pin can affect

the performance of the PLL This noise if in the 10 kHz to

400 kHz range can reduce the jitter performance of the

ENDEC resulting in missing packets or CRC errors If the

power supply noise is causing significant packet reception

error a low pass filter could be added to reduce the power

supply noise and hence improve the jitter performance

Standard analog design techniques should be utilized when

laying out the power supply traces on the board If the digital

power supply is used it may be desirable to add a one pole

RC filter (designed to have a cut-off frequency of 1 kHz) as

shown in

Figure 66 to improve the jitter performance The

PLLVCC only draws 3 mA–4 mA so the voltage across the

resistor is less than 90 mV which will not affect the PLL’s

operation

TLF10492 – 87

FIGURE 66 Filtering the Power Supply Noise

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