DP8422A datasheet(30/58 Pages) NSC

30 / 58 page

60 Port A Wait State Support (Continued)

TLF8588 – C2

FIGURE 24b WAITIN Example (WAIT is Sampled at the End of ‘‘T2’’)

64 GUARANTEEING RAS LOW TIME

AND RAS PRECHARGE TIME

The DP8420A21A22A will guarantee RAS precharge time

between accesses between refreshes and between ac-

cess and refreshes The programming bits R0 and R1 are

used to program combinations of RAS precharge time and

RAS low time referenced by positive edges of CLK RAS

low time is programmed for refreshes only During an ac-

cess the system designer guarantees the time RAS is as-

serted through the DP8420A21A22A wait logic Since in-

serting wait states into an access increases the length of

the CPU signals which are used to create ADS or ALE and

AREQ the time that RAS is asserted can be guaranteed

The

precharge

time

also

guaranteed

the

DP8420A21A22A Each RAS output has a separate posi-

tive edge of CLK counter AREQ is negated setup to a posi-

tive edge of CLK to terminate the access That positive

edge is 1T The next positive edge is 2T RAS will not be

asserted until the programmed number of positive edges of

CLK have passed as shown in

Figure 25 Once the pro-

grammed precharge time has been met RAS will be assert-

ed from the positive edge of CLK However since there is a

precharge counter per RAS an access using another RAS

will not be delayed Precharge time before a refresh is al-

ways referenced from the access RAS negating before

RAS0 for the refresh asserting After a refresh precharge

time is referenced from RAS3 negating for the refresh to

the access RAS asserting

TLF8588 – C3

FIGURE 25 Guaranteeing RAS Precharge (DTACK is Sampled at the ‘‘T2’’ Falling Clock Edge)

DP8422A Datasheet(PDF) 30 Page - National Semiconductor (TI)