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DP8422A Datasheet(PDF) 43 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP8422A
Description  microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers
PDF  58 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP8422A Datasheet(HTML) 43 Page - National Semiconductor (TI)

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130 AC Timing Parameters (Continued)
Unless otherwise stated VCC e 50V g10% 0 C k TA k 70 C the output load capacitance is typical for 4 banks of 18 DRAMs
per bank including trace capacitance (Note 2)
Two different loads are specified
CL e 50 pF loads on all outputs except
CL e 150 pF loads on Q0–8 9 10 and WE or
CH e 50 pF loads on all outputs except
CH e 125 pF loads on RAS0–3 and CAS0–3 and
CH e 380 pF loads on Q0–8 9 10 and WE
Common Parameter
8420A21A22A-20
8420A21A22A-25
Number
Symbol
Description
CL
CH
CL
CH
Min
Max
Min
Max
Min
Max
Min
Max
1fCLK
CLK Frequency
0
20
0
20
0
25
0
25
2
tCLKP
CLK Period
50
50
40
40
3 4
tCLKPW
CLK Pulse Width
15
15
12
12
5
fDCLK
DELCLK Frequency
5
20
5
20
5
20
5
20
6
tDCLKP
DELCLK Period
50
200
50
200
50
200
50
200
7 8
tDCLKPW
DELCLK Pulse Width
15
15
12
12
9a
tPRASCAS0
RAS Asserted to CAS Asserted
30
30
30
30
(tRAH e 15 ns tASC e 0 ns)
9b
tPRASCAS1
RAS Asserted to CAS Asserted
40
40
40
40
(tRAH e 15 ns tASC e 10 ns)
9c
tPRASCAS2
(RAS Asserted to CAS Asserted
40
40
40
40
(tRAH e 25 ns tASC e 0 ns)
9d
tPRASCAS3
(RAS Asserted to CAS Asserted
50
50
50
50
(tRAH e 25 ns tASC e 10 ns)
10a
tRAH
Row Address Hold Time (tRAH e 15)
15
15
15
15
10b
tRAH
Row Address Hold Time (tRAH e 25)
25
25
25
25
11a
tASC
Column Address Setup Time (tASC e 0)
0
0
0
0
11b
tASC
Column Address Setup Time (tASC e 10)
10
10
10
10
12
tPCKRAS
CLK High to RAS Asserted
27
32
22
26
following Precharge
13
tPARQRAS
AREQ Negated to RAS Negated
38
43
31
35
14
tPENCL
ECAS0 – 3 Asserted to CAS Asserted
23
31
20
27
15
tPENCH
ECAS0 – 3 Negated to CAS Negated
25
33
20
27
16
tPARQCAS
AREQ Negated to CAS Negated
60
68
47
54
17
tPCLKWH
CLK to WAIT Negated
39
39
31
31
18
tPCLKDL0
CLK to DTACK Asserted
(Programmed as DTACK of 12 1 1
33
33
28
28
or if WAITIN is Asserted)
19
tPEWL
ECAS Negated to WAIT Asserted
44
44
36
36
during a Burst Access
20
tSECK
ECAS Asserted Setup to CLK High to
Recognize the Rising Edge of CLK
24
24
19
19
during a Burst Access
43



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