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DP8422A Datasheet(PDF) 44 Page - National Semiconductor (TI) |
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DP8422A Datasheet(HTML) 44 Page - National Semiconductor (TI) |
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44 / 58 page  130 AC Timing Parameters (Continued) Unless otherwise stated VCC e 50V g10% 0 C k TA k 70 C the output load capacitance is typical for 4 banks of 18 DRAMs per bank including trace capacitance (Note 2) Two different loads are specified CL e 50 pF loads on all outputs except CL e 150 pF loads on Q0–8 9 10 and WE or CH e 50 pF loads on all outputs except CH e 125 pF loads on RAS0–3 and CAS0–3 and CH e 380 pF loads on Q0–8 9 10 and WE Common Parameter 8420A21A22A-20 8420A21A22A-25 Number Symbol Description CL CH CL CH Min Max Min Max Min Max Min Max 21 tPEDL ECAS Asserted to DTACK Asserted during a Burst Access 48 48 38 38 (Programmed as DTACK0) 22 tPEDH ECAS Negated to DTACK 49 49 38 38 Negated during a Burst Access 23 tSWCK WAITIN Asserted Setup to CLK 5 5 5 5 24 tPWINWEH WIN Asserted to WE Asserted 34 44 27 37 25 tPWINWEL WIN Negated to WE Negated 34 44 27 37 26 tPAQ Row Column Address Valid to 29 38 26 35 Q0 – 8 9 10 Valid 27 tPCINCQ COLINC Asserted to Q0 – 8 9 10 34 43 30 39 Incremented 28 tSCINEN COLINC Asserted Setup to ECAS 18 19 17 19 Asserted to Ensure tASC e 0ns 29a tSARQCK1 AREQ AREQB Negated Setup to CLK 46 46 37 37 High with 1 Period of Precharge 29b tSARQCK2 AREQ AREQB Negated Setup to CLK High 19 19 15 15 with l1 Period of Precharge Programmed 30 tPAREQDH AREQ Negated to DTACK Negated 34 34 27 27 31 tPCKCAS CLK High to CAS Asserted 31 39 25 32 when Delayed by WIN 32 tSCADEN Column Address Setup to ECAS 14 15 14 16 Asserted to Guarantee tASC e 0 33 tWCINC COLINC Pulse Width 20 20 20 20 34a tPCKCL0 CLK High to CAS Asserted following 81 89 72 79 Precharge (tRAH e 15 ns tASC e 0 ns) 34b tPCKCL1 CLK High to CAS Asserted following 91 99 82 89 Precharge (tRAH e 15 ns tASC e 10 ns) 34c tPCKCL2 CLK High to CAS Asserted following 91 99 82 89 Precharge (tRAH e 25 ns tASC e 0 ns) 34d tPCKCL3 CLK High to CAS Asserted following 101 109 92 99 Precharge (tRAH e 25 ns tASC e 10 ns) 35 tCAH Column Address Hold Time 32 32 32 32 (Interleave Mode Only) 36 tPCQR CAS Asserted to Row Address 90 90 90 90 Valid (Interleave Mode Only) 44 |
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