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DP8422A Datasheet(PDF) 46 Page - National Semiconductor (TI) |
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DP8422A Datasheet(HTML) 46 Page - National Semiconductor (TI) |
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46 / 58 page  130 AC Timing Parameters (Continued) Unless otherwise stated VCC e 50V g10% 0 C k TA k 70 C the output load capacitance is typical for 4 banks of 18 DRAMs per bank including trace capacitance (Note 2) Two different loads are specified CL e 50 pF loads on all outputs except CL e 150 pF loads on Q0–8 9 10 and WE or CH e 50 pF loads on all outputs except CH e 125 pF loads on RAS0–3 and CAS0–3 and CH e 380 pF loads on Q0–8 9 10 and WE Common Dual Access 8420A21A22A-20 8420A21A22A-25 Number Symbol Parameter Description CL CH CL CH Min Max Min Max Min Max Min Max 100 tHCKARQB AREQB Negated Held from CLK High 3 3 3 3 101 tSARQBCK AREQB Asserted Setup to CLK High 8 8 7 7 102 tPAQBRASL AREQB Asserted to RAS Asserted 43 48 37 41 103 tPAQBRASH AREQB Negated to RAS Negated 41 46 32 36 105 tPCKRASG CLK High to RAS Asserted for 55 60 44 48 Pending Port B Access 106 tPAQBATKBL AREQB Asserted to ATACKB Asserted 57 57 45 45 107 tPCKATKB CLK High to ATACKB Asserted 67 67 51 51 for Pending Access 108 tPCKGH CLK High to GRANTB Asserted 40 40 32 32 109 tPCKGL CLK High to GRANTB Negated 35 35 29 29 110 tSADDCKG Row Address Setup to CLK High That Asserts RAS following a GRANTB 11 15 11 16 Change to Ensure tASR e 0 ns for Port B 111 tSLOCKCK LOCK Asserted Setup to CLK Low 55 55 to Lock Current Port 112 tPAQATKBH AREQ Negated to ATACKB Negated 26 26 21 21 113 tPAQBCASH AREQB Negated to CAS Negated 59 67 47 54 114 tSADAQB Address Valid Setup to 711 7 12 AREQB Asserted 116 tHCKARQG AREQ Negated Held from CLK High 5 5 5 5 117 tWAQB AREQB High Pulse Width 31 35 26 31 to Guarantee tASR e 0ns 118a tPAQBCAS0 AREQB Asserted to CAS Asserted 103 111 87 94 (tRAH e 15 ns tASC e 0 ns) 118b tPAQBCAS1 AREQB Asserted to CAS Asserted 113 121 97 104 (tRAH e 15 ns tASC e 10 ns) 118c tPAQBCAS2 AREQB Asserted to CAS Asserted 113 121 97 104 (tRAH e 25 ns tASC e 0 ns) 118d tPAQBCAS3 AREQB Asserted to CAS Asserted 123 131 107 114 (tRAH e 25 ns tASC e 10 ns) 120a tPCKCASG0 CLK High to CAS Asserted for Pending Port B Access 113 121 96 103 (tRAH e 15 ns tASC e 0 ns) 120b tPCKCASG1 CLK High to CAS Asserted for Pending Port B Access 123 131 106 113 (tRAH e 15 ns tASC e 10 ns) 120c tPCKCASG2 CLK High to CAS Asserted for Pending Port B Access 123 131 106 113 (tRAH e 25 ns tASC e 0 ns) 120d tPCKCASG3 CLK High to CAS Asserted for Pending Port B Access 133 141 116 123 (tRAH e 25 ns tASC e 10 ns) 121 tSBADDCKG Bank Address Valid Setup to CLK High That Starts RAS 10 10 10 10 for Pending Port B Access 46 |
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