TMS320DM640 datasheet(90/171 Pages) TI

90 / 171 page

Enhanced Direct Memory Access (EDMA) Controller

June 2003 − Revised August 2004

SPRS222C

4.4

Enhanced Direct Memory Access (EDMA) Controller

The EDMA controller handles all data transfers between the level-two (L2) cache/memory controller and the

device peripherals on the DM641/DM640 DSP. These data transfers include cache servicing, non-cacheable

memory accesses, user-programmed data transfers, and host accesses.

4.4.1

EDMA Device-Specific Information

4.4.1.1

EDMA Channel Synchronization Events

The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.

Table 4−3 lists the source of C64x EDMA synchronization events associated with each of the programmable

EDMA channels. For the DM641/DM640 device, the association of an event to a channel is fixed; each of the

EDMA channels has one specific event associated with it. These specific events are captured in the EDMA

event registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL,

EERH). The priority of each event can be specified independently in the transfer parameters stored in the

EDMA parameter RAM. For more detailed information on the EDMA module and how EDMA events are

enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320C6000 DSP Enhanced

Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234).

Table 4−3. TMS320DM641/DM640 EDMA Channel Synchronization Events†

EDMA

CHANNEL

EVENT NAME

EVENT DESCRIPTION

DSP_INT

HPI-to-DSP interrupt [For DM641 Only; “None” for DM640]

TINT0

Timer 0 interrupt

TINT1

Timer 1 interrupt

SD_INTA

EMIFA SDRAM timer interrupt

GPINT4/EXT_INT4

GP0 event 4/External interrupt pin 4

GPINT5/EXT_INT5

GP0 event 5/External interrupt pin 5

GPINT6/EXT_INT6

GP0 event 6/External interrupt pin 6

GPINT7/EXT_INT7

GP0 event 7/External interrupt pin 7

GPINT0

GP0 event 0

GPINT1

GP0 event 1

GPINT2

GP0 event 2

GPINT3

GP0 event 3

XEVT0

McBSP0 transmit event

REVT0

McBSP0 receive event

XEVT1

McBSP1 transmit event

REVT1

McBSP1 receive event

VP0EVTYA

VP0 Channel A Y event DMA request

VP0EVTUA

VP0 Channel A Cb event DMA request

VP0EVTVA

VP0 Channel A Cr event DMA request

TINT2

Timer 2 interrupt

20−31

–

None

AXEVTE0

McASP0 transmit even event

AXEVTO0

McASP0 transmit odd event

AXEVT0

McASP0 transmit event

AREVTE0

McASP0 receive even event

† In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer

completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory

Access (EDMA) Controller Reference Guide (literature number SPRU234).

TMS320DM640 Datasheet(PDF) 90 Page - Texas Instruments

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