TMS320DM640 datasheet(113/171 Pages) TI

113 / 171 page

External Memory Interface (EMIIF)

113

June 2003 − Revised August 2004

SPRS222C

4.8.3.3

Synchronous DRAM Timing

Table 4−26. Timing Requirements for Synchronous DRAM Cycles for EMIFA Module (see Figure 4−22)

NO.

−400

−500

−600

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

tsu(EDV-EKO1H)

Setup time, read AEDx valid before AECLKOUTx high

2.1

0.6

th(EKO1H-EDV)

Hold time, read AEDx valid after AECLKOUTx high

2.5

1.8

Table 4−27. Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM

Cycles for EMIFA Module (see Figure 4−22−Figure 4−29)

NO.

PARAMETER

−400

−500

−600

UNIT

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

td(EKO1H-CEV)

Delay time, AECLKOUTx high to ACEx valid

1.3

6.4

1.3

4.9

td(EKO1H-BEV)

Delay time, AECLKOUTx high to ABEx valid

6.4

4.9

td(EKO1H-BEIV)

Delay time, AECLKOUTx high to ABEx invalid

1.3

td(EKO1H-EAV)

Delay time, AECLKOUTx high to AEAx valid

6.4

4.9

td(EKO1H-EAIV)

Delay time, AECLKOUTx high to AEAx invalid

1.3

td(EKO1H-CASV)

Delay time, AECLKOUTx high to ASDCAS valid

1.3

6.4

1.3

4.9

td(EKO1H-EDV)

Delay time, AECLKOUTx high to AEDx valid

6.4

4.9

td(EKO1H-EDIV)

Delay time, AECLKOUTx high to AEDx invalid

1.3

td(EKO1H-WEV)

Delay time, AECLKOUTx high to ASDWE valid

1.3

6.4

1.3

4.9

td(EKO1H-RAS)

Delay time, AECLKOUTx high to ASDRAS valid

1.3

6.4

1.3

4.9

td(EKO1H-ACKEV)

Delay time, AECLKOUTx high to ASDCKE valid

1.3

6.4

1.3

4.9

td(EKO1H-PDTV)

Delay time, AECLKOUTx high to APDT valid

1.3

6.4

1.3

4.9

TMS320DM640 Datasheet(PDF) 113 Page - Texas Instruments

TMS320DM640 Datasheet(HTML) 113 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL