LMP7312MASLASHNOPB datasheet(17/29 Pages) TI1

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LMP7312

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SNOSB32B – MARCH 2010 – REVISED MARCH 2013

Single Ended Output

In this mode the LMP7312 behaves as a Difference Amplifier, with -VOUT/VR being the reference output voltage

when a zero volt differential input signal is applied. The voltages at the OpAmp inputs are determined by +VIN

and -VOUT/VR voltages. The voltage range of +VIN and +IIN inputs is as follows:

VMAX = VS + 1/ KV * (VS – (-VOUT/VR))

VMIN = -1/KV * (-VOUT/VR)

Regardless of the values derived by the formula, the voltage on each input pin must never exceed the specified

Absolute Maximum Ratings.

Below are some typical values:

Table 3. Differential Input, Single Ended Output, VS = 5V, VOCM = GND, and -VOUT/VR = 2.5V

+VIN

+IIN

Gain

Min

Max

Min

Max

0.096 V/V

-15 V(1)

+15 V(1)

0.192 V/V

-11.5 V(1)

+15 V

0.384 V/V

-6 V

+11 V

0.768 V/V

-3.1 V

+8.1 V

1 V/V

-2.3 V

+7.3 V

2 V/V

-1.2 V

+6.2 V

(1)

Limited by the operating ratings on input pins

In the case of a single ended input referred to ground (-VIN = GND, -IN = GND) this table summarize the voltage

ranges allowed on the +VIN and +IIN inputs.

Table 4. Single Ended Input, Single Ended Output, VS = 5V, VOCM = GND, -VOUT/VR = 2.5V, -VIN = GND, -IIN =

GND

+VIN

+IIN

Gain

Min

Max

Min

Max

0.096 V/V

-15 V(1)

+15 V(1)

0.192 V/V

-11.5 V

+12 V(2)

0.384 V/V

-6 V(2)

+6 V(2)

0.768 V/V

-3 V**

+3 V(2)

1 V/V

-2.3 V(2)

+2.3 V(2)

2 V/V

-1.1 V(2)

+1.1 V(2)

(1)

Limited by the operating ratings on input pins.

(2)

Limited by the output voltage swing (0.2V to VS-0.2V on +VOUT )

SERIAL INTERFACE CONTROL OPERATION

The serial interface control of the LMP7312 can be supplied with a voltage between 2.7V and 5.5V through the

VIO pin for compatibility with different logic families present in the market.

The LMP7312 Attenuation, Amplification, Null switch and HiZ modes are controlled by a register. Data to be

written into the control register is first loaded into the LMP7312 via the serial interface. The serial interface

employs a 5-bit shift register. Data is loaded through the serial data input, SDI. Data passing through the shift

process. All five data bits are required to correctly program the device. The falling edge of CS enables the shift

the shift register on the rising edge of SCK. Data is transferred from the shift register to the holding register on

the rising edge of CS. Operation is shown in the Timing Diagram.

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