LMP8358MASLASHNOPB datasheet(21/40 Pages) TI1

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LOGIC

I/O LEVELS

VLSER/VHPAR

VHSER/VLPAR

V+

V-

PARALLEL MODE

SERIAL MODE

LMP8358

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SNOSB09B – APRIL 2010 – REVISED MARCH 2013

Figure 49. Communication Mode Selection.

PARALLEL CONTROL INTERFACE MODE

The LMP8358 is put into Parallel Mode by setting VLSER/VHPAR > VHSER/VLPAR. The register in the

LMP8358 does not control the settings of the LMP8358 in this mode. Gain and shutdown are set by placing a

high or low logic level on pins 11 (SHDN), 12 (G2), 13 (G1), and 14 (G0), as shown in Table 1 and Table 2. The

logic high and low levels are defined by the voltages on the VLSER/VHPAR and VHSER/VLPAR pins. See the

START UP AND POWER ON RESET section for power on requirements when using the parallel mode.

Table 1. Function of Digital IO Pins, Parallel Mode

Pin Name

Description

Gain setting (LSB)

Gain setting

Gain setting (MSB)

SHDN

Shutdown (Active High)

VHPAR

Positive logic level

VLPAR

Negative logic level

Table 2. Pin Levels for Setting Gain, Parallel Mode

Gain Setting

Bandwidth

Compen-

sation Setting (Auto-

matically

Set)

10x (power-up default)

930 kHz

000b

20x

385 kHz

000b

50x

460 kHz

001b

100x

640 kHz

010b

200x

195 kHz

010b

500x

130 kHz

011b

1000x

89 kHz

011b

User defined

800 kHz

1xxb

SERIAL CONTROL INTERFACE MODE

The LMP8358 is put into Serial Mode by setting VLSER/VHPAR < VHSER/VLPAR. In the Serial Mode the

LMP8358 can be programmed by using pins 11 – 14 as shown in Table 3 and the SPI Timing Diagram. The

LMP8358 contains a 16 bit register which controls the performance of the part. These bits can be changed using

the Serial Mode of communication. The register of the LMP8358 is shown in Table 4. Immediately after power on

the register should be written with the value needed for the application. See the START UP AND POWER ON

RESET section.

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