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LMP8358MA/NOPB Datasheet(PDF) 8 Page - Texas Instruments

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Part # LMP8358MA/NOPB
Description  Zero-Drift, Programmable Instrumentation Amplifier with Diagnostics
PDF  40 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

LMP8358MA/NOPB Datasheet(HTML) 8 Page - Texas Instruments

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LMP8358
SNOSB09B – APRIL 2010 – REVISED MARCH 2013
www.ti.com
5.0V Electrical Characteristics (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C. V
+ = 5.0V , V− = 0V, V
REF = V
+/2, V
CM = V
+/2, R
L = 10 kΩ to
VREF, CL = 10 pF; Serial Control Register: G[2:0] = 110b (Gain = 1000x), COMP[2:0] = 000b, MUX[1:0] = 00b, POL, SHDN,
FILT, PIN = 0b, CUR[2:0] = 000b. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min(1)
Typ(2)
Max(1)
Units
ITEST
Fault Detection: Test Current
Setting 1 (CUR[2:0] = 001b), VCM < V
+ −
10
nA
2.25V
Setting 2 (CUR[2:0] = 010b), VCM < V
+ −
100
nA
2.25V
Setting 3 (CUR[2:0] = 011b), VCM < V
+ −
1
µA
2.25V
Setting 4 (CUR[2:0] = 100b), VCM < V
+ −
10
µA
2.25V
Setting 5 (CUR[2:0] = 101b), VCM < V
+ −
100
µA
2.25V
Electrical Characteristics (Serial Interface)
Unless otherwise specified, all limits ensured for TA = 25°C, V
+ − V− ≥ 2.7V, V+ ≥ VHSER/VLPAR, V− ≤ VLSER/VHPAR, V
D =
(VHSER/VLPAR)
− (VLSER/VHPAR) ≥ 2.5V.
Symbol
Parameter
Conditions
Min(1)
Typ(2)
Max(1)
Units
VIL
Input Logic Low Threshold
0.3 × VD
V
VIH
Input Logic High Threshold
0.7 × VD
V
VOL
Output Logic Low Threshold
ISDO = 2mA
0.2
V
VOH
Output Logic High Threshold
ISDO = 2mA
VD − 0.2V
ISDO
Output Source Current, SDO
VD = 3.3V or 5.0V,
−2
CSB = 0V, VOH = V
+ – 0.7V
mA
Output Sink Current, SDO
VD = 3.3V or 5.0V,
2
CSB = 0V, VOL = 1.0V
IOZ
Output Tri-state Leakage Current,
VD = 3.3V or 5.0V,
±1
µA
SDO
CSB = VD = 3.3V or 5V
t1
High Period, SCK
(3)
100
ns
t2
Low Period, SCK
(3)
100
ns
t3
Set Up Time, CSB to SCK
(3)
50
ns
t4
Set Up Time, SDI to SCK
(3)
30
ns
t5
Hold Time, SCK to SDI
(3)
10
ns
t6
Prop. Delay, SCK to SDO
(3)
60
ns
t7
Hold Time, SCK Transition to CSB
(3)
50
ns
Rising Edge
t8
CSB Inactive
(3)
50
ns
t9
Prop. Delay, CSB to SDO Active
(3)
50
ns
t10
Prop. Delay, CSB to SDO Inactive
(3)
50
ns
t11
Hold Time, SCK Transition to CSB
(3)
10
ns
Falling Edge
tr/tf
Signal Rise and Fall Times
(3)
1.5
5
ns
(1)
All limits are specified by testing or statistical analysis.
(2)
Typical Values indicate the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3)
Load for these tests is shown in the Timing Diagram Test Circuit.
8
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