TAS5706APAPR datasheet(24/71 Pages) TI1

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2S Timing

SCLK

32Clks

LRCLK(NoteReversedPhase)

LeftChannel

24-BitMode

20-BitMode

16-BitMode

MSB

LSB

32Clks

RightChannel

2-ChannelI S(PhilipsFormat)StereoInput

T0034-01

MSB

LSB

SCLK

TAS5706A

TAS5706B

SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com

I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the

right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or

64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes

state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit

clock. The DAP masks unused trailing data bit positions.

NOTE: All data presented in 2s-complement form with MSB first.

Figure 30. I2S 64-fS Format

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Product Folder Link(s): TAS5706A TAS5706B

TAS5706A is Not Recommended for New Designs

TAS5706APAPR Datasheet(PDF) 24 Page - Texas Instruments

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