TAS5706APAPR datasheet(12/71 Pages) TI1

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SERIAL AUDIO PORTS SLAVE MODE

TAS5706A

TAS5706B

SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009............................................................................................................................................. www.ti.com

over recommended operating conditions (unless otherwise noted)

TEST

PARAMETER

MIN

TYP

MAX

UNIT

CONDITIONS

fSCLKIN

Frequency, SCLK 32 × fS, 48 × fS, 64 × fS

CL = 30 pF

1.024

12.288

MHz

tsu1

Setup time, LRCLK to SCLK rising edge

th1

Hold time, LRCLK from SCLK rising edge

tsu2

Setup time, SDIN to SCLK rising edge

th2

Hold time, SDIN from SCLK rising edge

LRCLK frequency

192

kHz

SCLK duty cycle

40%

50%

60%

LRCLK duty cycle

40%

50%

60%

SCLK

SCLK rising edges between LRCLK rising edges

edges

t(edge)

SCLK

LRCLK clock edge with respect to the falling edge of SCLK

–1/4

1/4

period

Figure 1. Slave Mode Serial Data Interface Timing

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Product Folder Link(s): TAS5706A TAS5706B

TAS5706A is Not Recommended for New Designs

TAS5706APAPR Datasheet(PDF) 12 Page - Texas Instruments

TAS5706APAPR Datasheet(HTML) 12 Page - Texas Instruments

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