LP8727

SNVS898A – OCTOBER 2012 – REVISED MAY 2013

www.ti.com

INTERRUPT STATUS

The LP8727 has 2 interrupt status registers, INT_STAT1 and INT_STAT2. These interrupt conditions are

generated from VBUS comparator, D+/D

− & ID detection, changes of SEND/END & MR_COMP states and

charger events. When any of these interrupt conditions occur, then the open drain output (INT\) will be brought

low. This signals to the BB processor that an interrupt has occurred. The BB processor will then read all two

INT_STAT1 and INT_STAT2 registers sequentially through the serial interface to determine which bit caused the

interrupt. Once the status register indicates the actual interrupt condition starts to be read, the INT\ output will be

brought high immediately. However, INT_STAT1 and INT_STAT2 registers will not be cleared after being read by

the BB processor and will always represent the current status.

INT\ OUTPUT

A serial interface read of each of the interrupt status registers immediately pulls up INT\ output. If an interrupt is

captured during a read sequence, the INT\ will not go low until at least 24 serial clocks (SCL) have occurred. Any

pending interrupts will be cleared once the LP8727 goes into SHUTDOWN mode.

DEVICE STATUS

The LP8727 has 2 device status registers, STATUS1 and STATUS2. These registers can be read via the serial

interface in much the same way as the interrupt status registers.

These registers will not be cleared on a read and will always represent the current state.

Device Identification

The LP8727 can recognize various accessories attached to Micro/Mini USB connector by detecting VBUS, D+,

D

− and ID pins. The detection comparators have a 60 ms of debounce timer. The device identification flow is

shown in Figure 4.

16

Submit Documentation Feedback

Copyright © 2012–2013, Texas Instruments Incorporated

Product Folder Links: LP8727