SDA

SCL

S

P

START CONDITION

STOP CONDITION

Data Line

Stable:

Data Valid

Change

of Data

Allowed

SDA

SCL

LP8727

SNVS898A – OCTOBER 2012 – REVISED MAY 2013

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DATA TRANSACTIONS

One data bit is transferred during each clock pulse. Data is sampled during the high state of the SCL.

Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the SDA line

during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data

should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

Figure 14. Bit Transfer

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a

Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following

sections provide further details of this process.

START AND STOP

The Master device on the bus always generates the Start-and-Stop Conditions (control codes). After a Start

Condition is generated, the bus is considered busy, and it retains this status until a certain time after a Stop

Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a

Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.

Figure 15. Start-and-Stop Conditions

In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction.

This allows another device to be accessed, or a register read cycle.

ACKNOWLEDGE CYCLE

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiving device. The master generates the acknowledge

clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go

high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the

acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus

signaling the correct reception of the last data byte and its readiness to receive the next byte.

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