LP8727

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SNVS898A – OCTOBER 2012 – REVISED MAY 2013

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If system voltage is higher than UVLO and OPVM, then UVLO_N state is set to '1'.

Using different values for UVLO and OPVM provides a window for voltage drops under high-load working

conditions.

UVLO_N state '0' indicates that the voltage is below normal working range, so the system is not allowed to start

up. This state can also cause the system to shut down.

UVLO_N state '1' indicates that the voltage is in normal working range, so the system is allowed to start up and

operate.

State transition '1'

→ '0' causes an UVLO interrupt, which can be sent to INT\ output.

Support Functions

REFERENCE

The LP8727 has internal reference block creating all necessary references and biasing for all blocks.

OSCILLATOR

There is internal oscillator giving clock to the logic control.

PARAMETER

TYP

MIN

MAX

UNIT

Oscillator Frequency

31

29

33

kHz

THERMAL SHUTDOWN

The thermal shutdown (TSHD) function monitors the chip temperature to protect the chip from temperature

damage caused by excessive power dissipation. When the chip temperature exceeds 160°C, “1” is written to

TSHD bit on INT_STAT2 register and INT\ is pulled to low and then the LP8727 will initiates SHUTDOWN. The

STARTUP operation after TSHD trigger can be initiated only after the chip has cooled down to the +115°C

threshold.

PARAMETER

TYP

UNIT

160

°C

45

(1)

specified by design.

CHIP TEMPERATURE MONITOR

The LP8727 supports the chip temperature monitoring feature. When the chip temperature reaches each

temperature threshold, TMP bit on INT_STAT2 will be set to “1”, and it will pull INT\ output low. The chip

temperature can be obtained by reading TMP_STAT bits on STATUS2 register.

TMP_STAT

000

001

010

011

TEMPERATURE

75°C

95°C

115°C

125°C

I

INTERFACE BUS OVERVIEW

the device.

This protocol uses a two-wire interface for bi-directional communications between the ICs connected to the bus.

The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). These lines should be

connected to a positive supply, via a pull-up resistor of 1.5 k

Ω and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on

whether it generates or receives the SCL.

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Product Folder Links: LP8727