Data

Output By

Transmitter

SCL

Start Condition

S

Data

Output By

Receiver

1

2

7

3 - 6

8

9

Acknowledgement Signal

from Receiver

Transmitter Stays Off the

Bus During the

Acknowledgement Clock

LP8727

www.ti.com

SNVS898A – OCTOBER 2012 – REVISED MAY 2013

Figure 16. Bus Acknowledge Cycle

”ACKNOWLEDGE AFTER EVERY BYTE” RULE

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge

signal after every byte received.

There is one exception to the “acknowledge after every byte” rule.

When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging

(“negative acknowledge”) the last byte clocked out of the slave. This “negative acknowledge” still includes the

acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

ADDRESSING TRANSFER FORMATS

Each device on the bus has a unique slave address. The slave address of the LP8727 is 7’h27 (0100111).

Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device

should send an acknowledge signal on the SDA line, once it recognizes its address.

The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends

on the bit sent after the slave address — the eighth bit. When the slave address is sent, each device in the

system compares this slave address with its own. If there is a match, the device considers itself addressed and

sends an acknowledge signal. Depending upon the state of the R/W bit (1: Read, 0: Write), the device acts as a

transmitter or a receiver.

CONTROL REGISTER WRITE CYCLE

•

Master device generates start condition.

•

Master device sends slave address (7 bits) and the data direction bit (r/w = '0').

•

Slave device sends acknowledge signal if the slave address is correct.

•

Master sends control register address (8 bits).

•

Slave sends acknowledge signal.

•

Master sends data byte to be written to the addressed register.

•

Slave sends acknowledge signal.

•

If master will send further data bytes the control register address will be incremented by one after

acknowledge signal.

•

Write cycle ends when the master creates stop condition.

CONTROL REGISTER READ CYCLE

•

Master device generates a start condition.

•

Master device sends slave address (7 bits) and the data direction bit (r/w = '0').

•

Slave device sends acknowledge signal if the slave address is correct.

•

Master sends control register address (8 bits).

•

Slave sends acknowledge signal.

•

Master device generates repeated start condition.

•

Master sends the slave address (7 bits) and the data direction bit (r/w = “1”).

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