TNETV2840ENGGU datasheet(37/91 Pages) TI1

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Functional Overview

December 1999 − Revised October 2008

SPRS122F

3.2.2.5

HPI Bus Holder Control

Both the HPI data and address buses have bus holders. By default, the bus holders are disabled after global

reset or subsystem A reset. The bus holders are configured via the BHD and BHA bits in the bank switching

control register (BSCR) located at 29h in subsystem A. Figure 3−13 shows the BSCR bit layout for

subsystem A and Table 3−5 describes the bit functions of BSCR.

Reserved

BHD

BHA

Reserved

R/W+0

LEGEND: R = Read, W = Write, U = Undefined

Figure 3−13. BSCR Register Bit Layout for Subsystem A

Table 3−5. BSCR Register Bit Functions for Subsystem A

BIT

NO.

BIT

NAME

FUNCTION

15−3

Reserved

These bits are reserved and are read as 0.

BHD

Data bus holder. BHD is cleared to 0 at reset.

BHD = 0: The HPI data bus holder is disabled.

BHD = 1: The HPI data bus holder is enabled.

BHA

Address bus holder. BHA is cleared to 0 at reset.

BHA = 0: The HPI address bus holder is disabled.

BHA = 1: The HPI address bus holder is enabled.

Reserved

This bit is reserved and is read as 0.

3.2.2.6

Other HPI16 System Considerations

•

Operation During IDLE − The HPI16 can continue to operate during IDLE1 or IDLE2 by using special clock

management logic that turns on relevant clocks to perform a synchronous memory access, and then turns

the clocks back off to save power. The DSP CPU does not wake up from the IDLE mode during this

process.

•

Downloading Code During Reset − The HPI16 can download code while the DSP is in reset. The system

provides a pin (RESET) that provides a way to take the HPI16 module out of reset while leaving the DSP

in reset.

•

Emulation considerations − The HPI16 can continue operation even when the DSP CPU is halted due to

debugger breakpoints or other emulation events.

•

XA Multiplexer − XA multiplexer controls the HPI data traffic from each subsystem to the device boundary.

The HPI module is the slave on the HPI bus. Figure 3−14 shows the 5441 block diagram with XA logic.

The XA basic function includes:

−

Making the HPI bus available for the selected subsystem HPI module according to HPI selection pins

HPI_SEL1/HPI_SEL2.

−

Granting HPI path to one of the subsystems at one time

•

The HPI_SEL1 and HPI_SEL2 pins are used to select the HPI module among the four cores. The selection

is indicated in Table 3−6.

TNETV2840ENGGU Datasheet(PDF) 37 Page - Texas Instruments

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