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TNETV2840ENGGU Datasheet(PDF) 61 Page - Texas Instruments

Part # TNETV2840ENGGU
Description  Fixed-Point Digital Signal Processor
PDF  91 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TNETV2840ENGGU Datasheet(HTML) 61 Page - Texas Instruments

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Functional Overview
61
December 1999 − Revised October 2008
SPRS122F
Figure 3−30 shows the bit layout of the IMR and the IFR. Table 3−27 describes the bit functions.
15
14
13
12
11
10
9
8
Reserved
DMAC5
DMAC4
XINT1 or
DMAC3
RINT1 or
DMAC2
HPINT
Reserved
R/W
R/W
R/W
R/W
R/W
76
54
32
10
XINT2 or
DMAC1
RINT2 or
DMAC0
XINT0
RINT0
TINT
Reserved
WDTINT
INT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R = Read, W = Write
Figure 3−30. Bit Layout of the IMR and IFR Registers for Each Subsystem
Table 3−27. Bit Functions for IMR and IFR Registers for Each DSP Subsystem
BIT
NO.
BIT
NAME
BIT
VALUE
FUNCTION
15−14
Reserved
X
Register bit is reserved.
13
DMAC5
0
IFR/IMR: DMA Channel 5 has no interrupt pending/is disabled (masked).
13
DMAC5
1
IFR/IMR: DMA Channel 5 has an interrupt pending/is enabled.
12
DMAC4
0
IFR/IMR: DMA Channel 4 has no interrupt pending/is disabled (masked).
12
DMAC4
1
IFR/IMR: DMA Channel 4 has an interrupt pending/is enabled.
XINT1
0
IFR/IMR: McBSP_1 has no transmit interrupt pending/is disabled (masked).
11
XINT1
1
IFR/IMR: McBSP_1 has a transmit interrupt pending/is enabled.
11
DMAC3
0
IFR/IMR: DMA Channel 3 has no interrupt pending/is disabled (masked).
DMAC3
1
IFR/IMR: DMA Channel 3 has an interrupt pending/is enabled.
RINT1
0
IFR/IMR: McBSP_1 has no receive interrupt pending/is disabled (masked).
10
RINT1
1
IFR/IMR: McBSP_1 has a receive interrupt pending/is enabled.
10
DMAC2
0
IFR/IMR: DMA Channel 2 has no interrupt pending/is disabled (masked).
DMAC2
1
IFR/IMR: DMA Channel 2 has an interrupt pending/is enabled.
9
HPINT
0
IFR/IMR: Host-port interface has no DSPINT interrupt pending/is disabled (masked).
9
HPINT
1
IFR/IMR: Host-port interface has an DSPINT interrupt pending/is enabled.
8
Reserved
X
Register bit is reserved.
XINT2
0
IFR/IMR: McBSP_2 has no transmit interrupt pending/is disabled (masked).
7
XINT2
1
IFR/IMR: McBSP_2 has a transmit interrupt pending/is enabled.
7
DMAC1
0
IFR/IMR: DMA Channel 1 has no interrupt pending/is disabled (masked).
DMAC1
1
IFR/IMR: DMA Channel 1 has an interrupt pending/is enabled.
RINT2
0
IFR/IMR: McBSP_2 has no receive interrupt pending/is disabled (masked).
6
RINT2
1
IFR/IMR: McBSP_2 has a receive interrupt pending/is enabled.
6
DMAC0
0
IFR/IMR: DMA Channel 0 has no interrupt pending/is disabled (masked).
DMAC0
1
IFR/IMR: DMA Channel 0 has an interrupt pending/is enabled.
5
XINT0
0
IFR/IMR: McBSP_0 has no receive interrupt pending/is disabled (masked).
5
XINT0
1
IFR/IMR: McBSP_0 has a receive interrupt pending/is enabled.
4
RINT0
0
IFR/IMR: McBSP_0 has no receive interrupt pending/is disabled (masked).
4
RINT0
1
IFR/IMR: McBSP_0 has a receive interrupt pending/is enabled.



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