TNETV2840ENGGU datasheet(68/91 Pages) TI1

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Electrical Specifications

December 1999 − Revised October 2008

SPRS122F

5.5.2 Multiply-By-N Clock Option − PLL Enabled

The frequency of the reference clock provided at the CLKIN pin can be multiplied by a factor of N to generate

the internal machine cycle. The selection of the clock mode and the value of N is described in Section 3.2.6.

Table 5−3 and Table 5−4 assume testing over recommended operating conditions and H = 0.5tc(CO) (see

Figure 5−3).

Table 5−3. Multiply-By-N Clock Option Timing Requirements

MIN

MAX

UNIT

Integer PLL multiplier N (N = 1−15)†

20‡

200

tc(CI)

Cycle time, CLKIN

PLL multiplier N = x.5†

20‡

100

tc(CI)

Cycle time, CLKIN

PLL multiplier N = x.25, x.75†

20‡

tf(CI)

Fall time, CLKIN

tr(CI)

Rise time, CLKIN

tw(CIL)

Pulse duration, CLKIN low

tw(CIH) Pulse duration, CLKIN high

† N = Multiplication factor

‡ The multiplication factor and minimum CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within the specified range

(tc(CO))

Table 5−4. Multiply-By-N Clock Option Switching Characteristics

PARAMETER

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, CLKOUT

7.5

tc(CI)/N†

td(CI-CO)

Delay time, CLKIN high/low to CLKOUT high/low

tf(CO)

Fall time, CLKOUT

1.5

tr(CO)

Rise time, CLKOUT

1.5

tw(COL)

Pulse duration, CLKOUT low

H−2

H−1

tw(COH)

Pulse duration, CLKOUT high

H−2

H−1

Transitory phase, PLL lock up time

† N = Multiplication factor

tc(CO)

tc(CI)

tw(COH)

tf(CO)

tr(CO)

tf(CI)

CLKIN

CLKOUT

td(CI-CO)

tw(COL)

tr(CI)

Unstable

tw(CIH)

tw(CIL)

Figure 5−3. External Multiply-by-One Clock Timing

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