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TNETV2840ENGGU Datasheet(PDF) 52 Page - Texas Instruments |
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TNETV2840ENGGU Datasheet(HTML) 52 Page - Texas Instruments |
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52 / 91 page ![]() Functional Overview 52 December 1999 − Revised October 2008 SPRS122F The lock timer is activated when the operating mode of the clock generator is switched from DIV to PLL. During the lockup period, the clock generator continues to operate in DIV mode; after the PLL lock timer decrements to zero, the PLL begins clocking the 5441. Accordingly, the value loaded into PLLCOUNT is chosen based on the following formula: PLLCOUNT + Lockup Time 16 T CLKIN where TCLKIN is the input reference clock period and lockup time is the required VCO lockup time, as shown in Table 3−17. Table 3−17. VCO Lockup Time CLKOUT FREQUENCY (MHz) LOCKUP TIME ( µs)† 5 23 10 17 20 16 40 19 60 24 80 29 100 35 135 45 † Approximate values 3.2.6.2 CLKMD Register Initialization At Reset The clock mode pin (CLKMD) is used to initialize the PLL to a known value at reset. The CLKMD pin is sampled when the reset signal is low. Only global reset (RESET) will reset the PLL. Subsystem A local reset (A_RS) has no effect on the PLL. Table 3−18. PLL Initialization at Reset CLKMD PIN PLL MODE 0 Bypass 1 CLKINx2 3.2.7 General-Purpose I/O The 5441 has 16 general-purpose I/O pins. These pins are: A_GPIO0, A_GPIO1, A_GPIO2, A_GPIO3 B_GPIO0, B_GPIO1, B_GPIO2, B_GPIO3 C_GPIO0, C_GPIO1, C_GPIO2, C_GPIO3 D_GPIO0, D_GPIO1, D_GPIO2, D_GPIO3 Four bits of general-purpose I/O are available to each core. Each GPIO pin can be individually selected as either an input or an output through the GPIO register. The x_XF, x_BIO, and timer output are selectable on GPIO pins 0, 1, and 3 through the GPIO register also. Each output driver has an independent three-state control. All nonreserved GPIO register bits are readable and writeable. The GPIO register bits will be set to 0 when the core is in reset, which will configure all GPIO as inputs. GPIO data and control bits are accessible through a memory-mapped register at 3Ch with the format shown in Figure 3−27 and the bit functions described in Table 3−19. |
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