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MCP2035-I/ST Datasheet(PDF) 53 Page - Microchip Technology |
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MCP2035-I/ST Datasheet(HTML) 53 Page - Microchip Technology |
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53 / 68 page ![]() 2012 Microchip Technology Inc. DS22304A-page 53 MCP2035 REGISTER 5-5: CONFIGURATION REGISTER 4 (ADDRESS: 0100) R/W-0 LCXSEN3 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LCXSEN2 LCXSEN1 LCXSEN0 0 0 0 0R4PAR bit7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 8-5 LCXSEN<3:0> : Typical Input Channel (LCX) Sensitivity Reduction bit. (Note 1) 0000 = -0 dB (Default) 0001 = -2 dB 0010 = -4 dB 0011 = -6 dB 0100 = -8 dB 0101 = -10 dB 0110 = -12 dB 0111 = -14 dB 1000 = -16 dB 1001 = -18 dB 1010 = -20 dB 1011 = -22 dB 1100 = -24 dB 1101 = -26 dB 1110 = -28 dB 1111 = -30 dB bit 4-1 Recommended to all 0’s. (Note 2) bit 0 R4PAR : Register 4 Parity bit – set or cleared (1 or 0) so the 9-bit register contains odd parity – an odd number of set bits. An incorrect parity bit may draw unnecessary extra current. Note 1: Assured monotonic increment (or decrement) by design. 2: These bits are associated to the internally grounded LCY sensitivity control, and have no effect in the MCP2035. |
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