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MCP2035-I/ST Datasheet(PDF) 55 Page - Microchip Technology |
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MCP2035-I/ST Datasheet(HTML) 55 Page - Microchip Technology |
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55 / 68 page ![]() 2012 Microchip Technology Inc. DS22304A-page 55 MCP2035 REGISTER 5-7: COLUMN PARITY REGISTER 6 (ADDRESS: 0110) R/W-0 COLPAR7 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 COLPAR6 COLPAR5 COLPAR4 COLPAR3 COLPAR2 COLPAR1 COLPAR0 R6PAR bit7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 8 COLPAR7 : Set or Cleared (1 or 0) so that this 8th parity bit (COLPAR7) + the sum of the Config. reg- ister row parity bits contain an odd number of set (“1”) bits. bit 7 COLPAR6 : Set or Cleared (1 or 0) such that this 7th parity bit (COLPAR6) + the sum of the 7th bits in Config. registers 0 through 5 contain an odd number of set (“1”) bits. bit 6 COLPAR5 : Set or Cleared (1 or 0) such that this 6th parity bit (COLPAR5) + the sum of the 6th bits in Config. registers 0 through 5 contain an odd number of set (“1” ) bits. bit 5 COLPAR4 : Set or Cleared (1 or 0) such that this 5th parity bit (COLPAR4) + the sum of the 5th bits in Config. registers 0 through 5 contain an odd number of set (“1”) bits. bit 4 COLPAR3 : Set or Cleared (1 or 0) such that this 4th parity bit (COLPAR3) + the sum of the 4th bits in Config. registers 0 through 5 contain an odd number of set (“1”) bits. bit 3 COLPAR2 : Set or Cleared (1 or 0) such that this 3rd parity bit (COLPAR2) + the sum of the 3rd bits in Config. registers 0 through 5 contain an odd number of set (“1”) bits. bit 2 COLPAR1 : Set or Cleared (1 or 0) such that this 2nd parity bit (COLPAR1) + the sum of the 2nd bits in Config. registers 0 through 5 contain an odd number of set (“1”) bits. bit 1 COLPAR0 : Set or Cleared (1 or 0) such that this 1st parity bit (COLPAR0) + the sum of the 1st bits in Config. registers 0 through 5 contain an odd number of set (“1”) bits. bit 0 R6PAR : Register 6 Parity bit – Set or Cleared (1 or 0) so the 9-bit register contains odd (“1”) parity – an odd number of set (“1”) bits Note 1: The parity bits are calculated from the configuration registers from 0 to 6 and programmed by the user. An incorrect parity bit can cause unnecessary extra current draws although the device may function correctly. |
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