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MAX1102 Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX1102 Datasheet(HTML) 8 Page - Maxim Integrated Products |
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8 / 16 page ![]() Detailed Description The MAX1102/MAX1103/MAX1104 are 8-bit CODECs in a compact 8-pin package. These devices consist of an 8-bit ADC, an 8-bit DAC, track/hold (T/H), DAC output buffer amplifier, internal voltage reference, input multi- plexer (mux) and a 6MHz SPI, QSPI and MICROWIRE compatible 4-wire serial interface. A single 8-bit word configures the MAX1102/MAX1103/MAX1104, provid- ing a simple interface to a microcontroller (µC). Analog-to-Digital Converter The MAX1102/MAX1103/MAX1104 ADC section uses a successive-approximation (SAR) conversion technique and input T/H circuitry to convert an analog signal to an 8-bit digital output. No external hold capacitors are required. The MAX1102/MAX1103 have an input multi- plexer that directs either AIN or VDD/2 to the input of the T/H, allowing these devices to either convert the analog input, or monitor the power supply. Figure 1 shows the detailed functional diagram of the ADC block. ADC Operation The input architecture of the ADC is illustrated in Figure 2, the equivalent input circuit, and is composed of the T/H, input mux (MAX1102/MAX1103), input comparator, switched capacitor DAC, and the auto-zero rail. The switched capacitor DAC is independent of the R-2R ladder DAC and does not provide the converted analog output on OUT. The T/H is in hold mode while a conversion is taking place. Once the conversion is completed, the T/H enters acquisition mode, and tracks the input signal until the start of the next conversion. In single conver- sion mode, conversion starts at the falling clock edge corresponding to the last bit of the control word. In con- tinuous conversion mode, the first conversion following the control word starts on the falling clock edge of the 8-Bit CODECs 8 _______________________________________________________________________________________ Pin Description PIN NAME FUNCTION 1VDD Voltage Supply 2 GND Ground 3 AIN ADC Analog Input 4 OUT DAC Analog Voltage Output 5 CS Chip Select Input. Device ignores all logic signals when CS is high. 6 SCLK Serial Clock Input. Data in is latched on the rising edge, data out transitions on the falling edge. 7 DOUT ADC Digital Output. Output is high impedance when CS is high. 8 DIN DAC Digital Input. Input ignores all signals when CS is high. DIN ANALOG INPUT MUX ANALOG INPUT MUX CONTROL LOGIC/2 AIN VDD/2 T/H SCLK CS MAX1102 MAX1103 SUCCESSIVE APPROXIMATION REGISTER INTERNAL OSCILLATOR INTERNAL OSCILLATOR DOUT CHARGE REDISTRIBUTION DAC OUTPUT SHIFT REGISTER Figure 1. ADC Detailed Functional Diagram |
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