OPA690IDBVT datasheet(19/22 Pages) TI

19 / 22 page

OPA690

SBOS223A

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a) Minimize parasitic capacitance to any AC ground for all

of the signal I/O pins. Parasitic capacitance on the output and

inverting input pins can cause instability: on the noninverting

input, it can react with the source impedance to cause

unintentional bandlimiting. To reduce unwanted capacitance,

a window around the signal I/O pins should be opened in all

of the ground and power planes around those pins. Other-

wise, ground and power planes should be unbroken else-

where on the board.

b) Minimize the distance (< 0.25") from the power-supply

pins to high-frequency 0.1

µF decoupling capacitors. At the

device pins, the ground and power plane layout should not

be in close proximity to the signal I/O pins. Avoid narrow

power and ground traces to minimize inductance between

the pins and the decoupling capacitors. The power-supply

connections should always be decoupled with these capaci-

tors. An optional supply decoupling capacitor (0.1

µF) across

the two power supplies (for bipolar operation) will improve

2nd-harmonic distortion performance. Larger (2.2

µF to 6.8µF)

decoupling capacitors, effective at lower frequency, should

also be used on the main supply pins. These may be placed

somewhat farther from the device and may be shared among

several devices in the same area of the PC board.

c) Careful selection and placement of external compo-

nents will preserve the high-frequency performance of

the OPA690. Resistors should be a very low reactance type.

Surface-mount resistors work best and allow a tighter overall

layout. Metal film or carbon composition axially-leaded resis-

tors can also provide good high-frequency performance.

Again, keep their leads and PC board traces as short as

possible. Never use wirewound type resistors in a high-

frequency application. Since the output pin and inverting

input pin are the most sensitive to parasitic capacitance,

always position the feedback and series output resistor, if

any, as close as possible to the output pin. Other network

components, such as noninverting input termination resis-

tors, should also be placed close to the package. Where

double-side component mounting is allowed, place the feed-

back resistor directly under the package on the other side of

the board between the output and inverting input pins. Even

with a low parasitic capacitance shunting the external resis-

tors, excessively high resistor values can create significant

time constants that can degrade performance. Good axial

metal film or surface-mount resistors have approximately

0.2pF in shunt with the resistor. For resistor values > 1.5k

Ω,

this parasitic capacitance can add a pole and/or zero below

500MHz that can effect circuit operation. Keep resistor val-

ues as low as possible consistent with load driving consider-

ations. The 402

Ω feedback used in the Electrical Character-

istics is a good starting point for design. Note that a 25

Ω

feedback resistor, rather than a direct short, is suggested for

the unity-gain follower application. This effectively isolates

the inverting input capacitance from the output pin that would

otherwise cause an additional peaking in the gain of +1

frequency response.

The transition edge rate (dv/dt) of the DIS control line will

influence this glitch. For the plot of Figure 14, the edge rate

was reduced until no further reduction in glitch amplitude was

observed. This approximately 1V/ns maximum slew rate may

be achieved by adding a simple RC filter into the DIS pin

from a higher speed logic line. If extremely fast transition

logic is used, a 1k

Ω series resistor between the logic gate

and the DIS input pin will provide adequate bandlimiting

using just the parasitic input capacitance on the DIS pin

while still ensuring adequate logic level swing.

THERMAL ANALYSIS

Due to the high output power capability of the OPA690,

heatsinking or forced airflow may be required under extreme

operating conditions. Maximum desired junction temperature

will set the maximum allowed internal power dissipation as

described below. In no case should the maximum junction

temperature be allowed to exceed 175

°C.

Operating junction temperature (TJ) is given by TA + PD • θJA.

The total internal power dissipation (PD) is the sum of

quiescent power (PDQ) and additional power dissipated in the

output stage (PDL) to deliver load power. Quiescent power is

simply the specified no-load supply current times the total

supply voltage across the part. PDL will depend on the

required output signal and load but would, for a grounded

resistive load, be at a maximum when the output is fixed at

a voltage equal to 1/2 of either supply voltage (for equal

bipolar supplies). Under this condition, PDL = VS2/(4 • RL)

where RL includes feedback network loading.

Note that it is the power in the output stage and not into the

load that determines internal power dissipation.

As a worst-case example, compute the maximum TJ using an

OPA690IDBV (SOT23-6 package) in the circuit of Figure 1

operating at the maximum specified ambient temperature of

+85

°C and driving a grounded 20Ω load.

PD = 10V • 6.2mA + 52/(4 • (20Ω || 804Ω)) = 382mW

Maximum TJ = +85°C + (0.38W • 150°C/W) = 142°C.

Although this is still well below the specified maximum

junction temperature, system reliability considerations may

require lower tested junction temperatures. The highest pos-

sible internal dissipation will occur if the load requires current

to be forced into the output for positive output voltages or

sourced from the output for negative output voltages. This

puts a high current through a large internal voltage drop in

the output transistors. The output V-I plot shown in the

Typical Characteristics include a boundary for 1W maximum

internal power dissipation under these conditions.

BOARD LAYOUT GUIDELINES

Achieving optimum performance with a high-frequency am-

plifier like the OPA690 requires careful attention to board

layout parasitics and external component types. Recommen-

dations that will optimize performance include:

OPA690IDBVT Datasheet(PDF) 19 Page - Texas Instruments

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