DS1744 datasheet(5/18 Pages) DALLAS

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DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs

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Table 2. Register Map

DATA

ADDRESS

FUNCTION RANGE

7FFFF

10 Year

Year

00-99

7FFFE

10 Month

Month

01-12

7FFFD

10 Date

Date

01-31

7FFFC

Day

01-07

7FFFB

10 Hour

Hour

00-23

7FFFA

10 Minutes

Minutes

00-59

7FFF9

OSC

10 Seconds

Seconds

00-59

7FFF8

10 Century

Century

00-39

OSC = Stop Bit

R = Read Bit

FT = Frequency Test

W = Write Bit

X = See Note

BF = Battery Flag

NOTE: All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.

RETRIEVING DATA FROM RAM OR CLOCK

The DS1744 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and

CE (chip enable) is low. The device architecture allows ripple-through access to any of the address

locations in the NV SRAM. Valid data is available at the DQ pins within tAA after the last address input is

stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and

states are not met, valid data is available at the latter of chip-enable access (tCEA) or at output-enable access

time (tOEA). The state of the DQ pins is controlled by CE and OE . If the outputs are activated before tAA,

the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and

OE remain valid, output data remains valid for output-data hold time (tOH) but then goes indeterminate

until the next address access.

WRITING DATA TO RAM OR CLOCK

The DS1744 is in the write mode whenever WE and CE are in their active state. The start of a write is

referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout

the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or

write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a

typical application, the OE signal is high during a write cycle. However, OE can be active provided that

care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low, the

data bus can become active with read data defined by the address inputs. A low transition on WE then

disables the output tWEZ after WE goes active.

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