PLL1700

2

SBOS096A

www.ti.com

PIN ASSIGNMENTS

PIN CONFIGURATION

TOP VIEW

SSOP

SPECIFIED

TEMPERATURE

PACKAGE

PRODUCT

PACKAGE

RANGE

DESIGNATOR

PLL1700E

20-Lead SSOP

–25

°C to +85°CDB

NOTE: (1) For the most current package and ordering information, see the

Package Option Addendum at the end of this data sheet, or see the TI web

site at www.ti.com.

GND Voltage Differences: GND, GNDP, GNDB ...............................

±0.1V

Input Current (any pins except supply pins) ...................................

±10mA

Power Dissipation .......................................................................... 300mW

Operating Temperature Range ......................................... –25

°C to +85°C

Storage Temperature ...................................................... –55

°C to +125°C

Lead Temperature (soldering, 5s) .................................................. +260

°C

Package Temperature (IR reflow, 10s) .......................................... +235

°C

NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may

cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

PIN

NAME

I/O

FUNCTION

1

ML/SR0

IN

Latch Enable for Software Mode/Sampling Rate

Selection for Hardware Mode. When MODE pin

2

MODE

IN

Mode Control Select. When this pin is HIGH,

device is operated in hardware mode using SR0

(pin 1), FS0 (pin 19), and FS1 (pin 20). When

this pin is LOW, device is operated in software

mode by three-wire interface using ML (pin 1),

—

Digital Power Supply, +5V.

4

GND

—

Digital Ground.

5

XT2

—

27MHz Crystal. When an external 27MHz clock

is applied to XT1 (pin 6), this pin must be

connected to GND.

6

XT1

IN

27MHz Oscillator Input/External 27MHz Input.

7

GNDP

—

Ground for PLL.

—

Power Supply for PLL, +5V.

9

RSV

—

Reserved. Must be left open.

10

MCKO

OUT

27MHz Output.

11

MCKO

OUT

Inverted 27MHz Output.

12

SCKO1

OUT

Fixed 33.8688MHz Clock Output.

13

SCKO4

OUT

14

SCKO2

OUT

15

GNDB

—

16

—

Digital Power Supply for Clock Output Buffers,

+3.3V.

17

SCKO3

OUT

for the lowest jitter and should be connected to

the audio DAC(s).

18

RST

IN

Reset. When this pin is LOW, device is held in

19

MD/FS0

IN

Serial Data Input for Software Mode/Sampling

Frequency Selection for Hardware Mode. When

20

MC/FS1

IN

Shift Clock Input for Software Mode/Sampling

Frequency Selection for Hardware Mode. When

NOTE: (1) Schmitt-trigger input with internal pull-down resistors.

ML/SR0

MODE

V

DD

GND

XT2

XT1

GNDP

V

DDP

RSV

MCKO

MC/FS1

MD/FS0

RST

SCKO3

V

DDB

GNDB

SCKO2

SCKO4

SCKO1

MCKO

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

PLL1700E

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be

handled with appropriate precautions. Failure to ob-

serve proper handling and installation procedures can

cause damage.

ESD damage can range from subtle performance deg-

radation to complete device failure. Precision integrated

circuits may be more susceptible to damage because

very small parametric changes could cause the device

not to meet its published specifications.