PLL1700ESLASH2K datasheet(5/15 Pages) TI1

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PLL1700

SBOS096A

www.ti.com

THEORY OF OPERATION

MASTER CLOCK AND SYSTEM CLOCK OUTPUT

The PLL1700 consists of a dual PLL clock and master

clock generator which generates four system clocks and

two buffered 27MHz clocks from a 27MHz master clock.

Figure 1 shows the block diagram of the PLL1700. The

PLL is designed to accept a 27MHz master clock or

crystal oscillator. The master clock can be either a crystal

oscillator placed between XT1 (pin 6) and XT2 (pin 5), or

an external input to XT1. If an external master clock is

used, XT2 must be connected to ground. In both cases,

the signal amplitude on XT1 must satisfy the specification

described in Figure 3. Therefore, careful C1 and C2

determination is required for keeping this specification

when using a crystal oscillator.

Figure 2 illustrates possible system clock connection

options. Figure 3 illustrates the 27MHz master clock

timing requirements.

FIGURE 1. Block Diagram of PLL1700.

FIGURE 2. Master Clock Generator Connection Diagram.

FIGURE 3. External Master Clock Timing Requirement.

XT1H

XT1L

1.2V

XT1

0.4V

DESCRIPTION

SYMBOL

MIN

TYP

MAX

UNITS

System Clock Pulse Width HIGH

tXT1H

System Clock Pulse Width LOW

tXT1L

OSC

Counter N

Counter M

Counter P

Counter Q

SCKO2

256f

SCKO1

33.8688MHz

SCKO4

768f

SCKO3

384f

Data

ROM

Frequency Control

PLL2

PLL1

Phase Detector

and

Loop Filter

VCO

Counter M

Counter N

Phase Detector

and

Loop Filter

MCKO

27MHz

MCKO

XT2

XT1

1, C2 = 10pF to 33pF

27MHz Internal

Master Clock

XTI

XT2

Crystal

OSC

Circuit

Xtal

PLL1700

MCKO

Buffer

External Clock

Crystal Resonator Connection

MCKO

Buffer

Crystal

OSC

Circuit

27MHz Internal

Master Clock

XT1

XT2

PLL1700

MCKO

Buffer

External Clock Input

MCKO

Buffer

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