Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

PLL1700E/2K Datasheet(PDF) 8 Page - Texas Instruments

Click here to check the latest version.
Part # PLL1700E/2K
Description  MULTI-CLOCK GENERATOR
PDF  15 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

PLL1700E/2K Datasheet(HTML) 8 Page - Texas Instruments

Back Button PLL1700E/2K Datasheet HTML 4Page - Texas Instruments PLL1700E/2K Datasheet HTML 5Page - Texas Instruments PLL1700E/2K Datasheet HTML 6Page - Texas Instruments PLL1700E/2K Datasheet HTML 7Page - Texas Instruments PLL1700E/2K Datasheet HTML 8Page - Texas Instruments PLL1700E/2K Datasheet HTML 9Page - Texas Instruments PLL1700E/2K Datasheet HTML 10Page - Texas Instruments PLL1700E/2K Datasheet HTML 11Page - Texas Instruments PLL1700E/2K Datasheet HTML 12Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 15 page
background image
PLL1700
8
SBOS096A
www.ti.com
FIGURE 8. Software Mode Control Format.
FS1
FS0
SAMPLING FREQUENCY
DEFAULT
0
0
48kHz
O
0
1
44.1kHz
1
0
32kHz
1
1
Reserved
PROGRAM REGISTER BIT-MAPPING
The built-in functions of the PLL1700 are controlled through
a 16-bit program register. This register is loaded using
MD. After the 16 data bits are clocked in using the rising
edge of MC, ML is used to latch the data into the register.
Table V shows the bit-mapping of the registers. The
software mode control format and control data input
timing is shown in Figures 8 and 9, respectively.
Mode Register
CE [1:6]:
Clock Output Control
DESCRIPTION
SYMBOL
MIN
TYP
MAX
UNITS
MC Pulse Cycle Time
tMCY
100
ns
MC Pulse Width LOW
tMCL
40
ns
MC Pulse Width HIGH
tMCH
40
ns
MD Hold Time
tMDH
40
ns
MD Set-Up Time
tMDS
40
ns
ML Low Level Time
tMLL
16
MC Clocks(1)
ML High Level Time
tMHH
200
ns
ML Hold Time(2)
tMLH
40
ns
ML Set-Up Time(3)
tMLS
40
ns
NOTES: (1) MC clocks: MC clock period. (2) MC rising edge for LSB to ML rising edge. (3) ML rising edge
to the next MC rising edge. If the MC Clock is stopped after the LSB, any ML rising time is accepted.
FIGURE 9. Control Data Input Timing.
REGISTER
BIT NAME
DESCRIPTION
MODE
CE6
MCKO Output Enable/Disable
CE5
MCKO Output Enable/Disable
CE4
SCKO4 Output Enable/Disable
CE3
SCKO3 Output Enable/Disable
CE2
SCKO2 Output Enable/Disable
CE1
SCKO1 Output Enable/Disable
SR [1:0]
Sampling Rate Select
FS [1:0]
Sampling Frequency Select
TABLE V. Register Mapping.
Mode Register
FS [1:0]:
Sampling Frequency Group Select. This se-
lection must be made with an interval time
greater than 20
µs.
SR [1:0]:
Sample Rate Select
SR1
SR0
SAMPLING RATE
DEFAULT
0
0
Standard
O
0
1
Double
1
0
Reserved
1
1
Reserved
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ML (pin 1)
MC (pin 20)
MD (pin 19)
D15 D14 D13 D12 D11 D0 D9
D8
D7
D6D5D4
D3D2D1
D0
0
1
1
1
0
0
CE6 CE5 CE4 CE3 CE2 CE1 SR1 SR0 FS1 FS0
CE1 - CE6
CLOCK OUTPUT CONTROL
DEFAULT
0
Clock Output Disable
1
Clock Output Enable
O
MSB
LSB
1.4V
1.4V
1.4V
t
MLS
t
MCH
t
MCL
t
MLL
t
MHH
t
MLH
t
MLS
t
MDS
t
MDH
t
MCY
ML (pin 1)
MC (pin 20)
MD (pin 19)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com