PLL1700

6

SBOS096A

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The PLL1700 provides a very low jitter, high accuracy

clock. SCKO1 is a fixed frequency clock which is

33.8688MHz (768 x 44.1kHz) for a CD-DA DSP. The

output frequency of the remaining clocks is determined by

sampling frequency is 32kHz, 44.1kHz, 48kHz, or the

or 96kHz. Table I shows each sampling frequency. The

system clock output frequencies are generated by a

27MHz master clock and programmed sampling frequen-

cies are shown in Table II.

SAMPLING

FREQUENCY

SAMPLING

SKCO2

SCKO3

SCKO4

(kHz)

RATE

(MHz)

(MHz)

(MHz)

32

Standard

8.192

12.288

24.576

44.1

Standard

11.2896

16.9344

33.8688

48

Standard

12.288

18.4320

36.8640

64

Double

16.384

24.576

24.576

88.2

Double

22.5792

33.8688

33.8688

96

Double

24.576

36.8640

36.8640

TABLE II. Sampling Frequencies and Master Clock

Output Frequencies.

SAMPLING

SAMPLING RATE

FREQUENCY (kHz)

Standard Sampling Frequencies

32

44.1

48

Double of Standard Sampling Frequencies

64

88.2

96

TABLE I. Sampling Frequencies.

FUNCTION CONTROL

The built-in function of the PLL1700 can be controlled in

the software mode (serial mode), which uses a three-wire

interface by ML (pin 1), MC (pin 20), and MD (pin 19), when

MODE (pin 2) = L. They can also be controlled in the

hardware mode (parallel mode) which uses SR0 (pin 1),

FS1 (pin 20) and FS0 (pin 19), when MODE (pin 2) = H.

The selectable functions are shown in Table III.

HARDWARE

SOFTWARE

MODE

MODE

FUNCTION

(MODE = H)

(MODE = L)

Sampling Frequency Select

(32kHz, 44.1kHz, 48kHz)

Yes

Yes

Sampling Rate Select (Standard/Double)

Yes

Yes

Each Clock Output Enable/Disable

No

Yes

TABLE III. Selectable Functions.

Response time from power-on (or applying the clock to

XT1) to SCKO settling time is typically 15ms. Delay time

from sampling frequency change to SCKO settling time is

20ms maximum. Figure 4 illustrates SCKO transient

timing.

External buffers are recommended on all output clocks in

order to avoid degrading the jitter performance of the

PLL1700.

RESET

The PLL1700 has an internal power-on reset circuit, as

well as an external forced reset (RST, pin 18). Both resets

have the same effect on the PLL1700 functions. The

mode register default settings for software mode are

initialized by reset. Throughout the reset period, all clock

outputs are enabled with the default settings. Initialization

for the internal power-on reset is done automatically

When using the internal power-on reset, RST should be

HIGH. Power-on reset timing is shown in Figure 5. RST

(pin 18) accepts an external forced reset by RST = L.

Initialization (reset) is done when

RST = L and 1024

master clocks after RST = H. External reset timing is

shown in Figures 6 and 7.

FUNCTION

DEFAULT

Sampling Frequency Select (32kHz, 44.1kHz, 48kHz)

48kHz Group

Sampling Rate Select (Standard/Double)

Standard

Each Clock Output Enable/Disable

Enable

TABLE IV. Selectable Functions.

FS1 (Pin 20)

FS0 (Pin 19)

SAMPLING GROUP

L

L

48kHz

L

H

44.1kHz

H

L

32kHz

H

H

Reserved

SR0 (Pin 1)

SAMPLING RATE SELECT

L

Standard

H

Double

HARDWARE MODE (MODE = H)

In the hardware mode, the following functions can be

selected:

Sampling Group Select

The sampling frequency group can be selected by FS1

(pin 20) and FS0 (pin 19). This selection must be made

with an interval time greater than 20

µs.

Sampling Rate Select

The sampling rate can be selected by SR0 (pin 1).

SOFTWARE MODE (MODE = L)

The PLL1700 special function in software mode is shown

in Table IV. These functions are controlled using ML, MC,

and MD serial control signal.