© VITESSE SEMICONDUCTOR CORPORATION

Page 5

9/14/98

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC8162

2.488 Gbit/sec SONET/SDH

1:16 Demux with Clock Recovery

G52209-0, Rev. 2.0

Interface Recommendations

REFCK+, REFCK– Inputs

Internal biasing will position the reference voltage of approximately -1.32V on both the true and comple-

ment inputs. This input can either be DC coupled or AC coupled; it can also be driven single-ended or differen-

tially. Figure 2 shows the configuration for single-ended, AC-coupling operation. In the case of direct coupling

input.

Figure 2: Single-ended AC Coupling for REFCK+, REFCK– Inputs

REFCK+

REFCK–

-1.32V

-1.32V

Chip Boundary

selected for REFCLK = 19.44 MHz)

(Capacitor values are