© VITESSE SEMICONDUCTOR CORPORATION

Page 7

9/14/98

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC8162

2.488 Gbit/sec SONET/SDH

1:16 Demux with Clock Recovery

G52209-0, Rev. 2.0

High Speed Clock Output

The high speed clock output is provided for test and measurement purposes. A termination method for the

high speed clock output is shown in Figure 5. In addition to the AC coupling method shown, the device may

also be DC coupled with a 50

Ω resistor connected to V

age swing of 200mV - 300mV, single-ended peak-to-peak, can be expected.

In order to reduce noise on the board, the clock output can be disabled by using the CKOE pin. CKOE is a

normal ECL input, which, when left floating, will default to a low level (output disabled). In order to set the

Figure 5: High-Speed Clock Output Termination

CLK

CLKN

8162

270

Ω

0.1 uF

0.1 uF

50

Ω

50

Ω

270

Ω