ASX340AT datasheet(36/54 Pages) ONSEMI

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ASX340AT

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Figure 31 shows detailed vertical blanking information

for PAL timing. See Table 25 for data on field, vertical

blanking, EAV, and SAV states.

Figure 36. Typical CCIR656 Vertical Blanking Intervals for 625/50 Video System

Blanking

Field 1 Active Video

Blanking

Field 2 Active Vi

deo

Field 1

(F = 0)

Odd

Field 2

(F =

H =

Blanking

Line 1 (V = 1)

Line 2 3 (V = 0)

Line 311 (V = 1)

Line 336 (V = 0)

Line 625 (V = 1)

Line 62 4 (V = 1)

TABLE 28. FIELD, VERTICAL BLANKING, EAV, AND SAV STATES FOR 625/50 VIDEO SYSTEM

Line Number

H (EAV)

H (SAV)

1–22

23–310

311–312

313–335

336–623

624–625

Reset and Clocks

Reset

Power-up reset is asserted or de-asserted with the

RESET_BAR pin, which is active LOW. In the reset state,

all control registers are set to default values. See “Device

Configuration” for more details on Auto, Host, and Flash

configurations.

Soft reset is asserted or de-asserted by the two-wire serial

interface. In soft-reset mode, the two-wire serial interface

and the register bus are still running. All control registers are

reset using default values.

Clocks

The ASX340AT has two primary clocks:

• A master clock coming from the EXTCLK signal.

• In default mode, a pixel clock (PIXCLK) running at

2 * EXTCLK. In raw Bayer bypass mode, PIXCLK

runs at the same frequency as EXTCLK.

When the ASX340AT operates in raw Bayer bypass

mode, the image flow pipeline clocks can be shut off to

conserve power.

The sensor core is a master in the system. The sensor core

frame rate defines the overall image flow pipeline frame

rate. Horizontal blanking and vertical blanking are

influenced by the sensor configuration, and are also a

function of certain image flow pipeline functions. The

relationship of the primary clocks is depicted in Figure 32.

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